A package structure includes a semiconductor die, a plurality of conductive features, a bridge structure, an underfill, via structures and an encapsulant. The conductive features are electrically connected to the semiconductor die, wherein the conductive features include a first group with planar top surfaces, and a second group with uneven top surfaces. The bridge structure is partially overlapped with the semiconductor die and electrically connected to the first group of the conductive feature. The underfill is covering and contacting the first group of the conductive features. The via structures are disposed on and overlapped with the semiconductor die and electrically connected to the second group of the conductive features. The encapsulant is covering and contacting the via structures and the second group of the conductive features.

A semiconductor device structure is provided. The semiconductor device structure includes an isolation structure formed over a substrate, and a first stacked nanostructure and a second stacked nanostructure extending above the isolation structure. The semiconductor device structure includes an inner spacer layer surrounding the first stacked nanostructure, and a dummy fin structure formed over the isolation structure. The dummy fin structure is between the first stacked nanostructure and the second stacked nanostructure, and a capping layer formed over the dummy fin structure. The inner spacer layer is in direct contact with the dummy fin structure and the capping layer.

Embodiments herein are generally directed to methods of forming high aspect ratio metal contacts and/or interconnect features, e.g., tungsten features, in a semiconductor device. Often, conformal deposition of tungsten in a high aspect ratio opening results in a seam and/or void where the outward growth of tungsten from one or more walls of the opening meet. Thus, the methods set forth herein provide for a desirable bottom up tungsten bulk fill to avoid the formation of seams and/or voids in the resulting interconnect features, and provide an improved contact metal structure and method of forming the same. In some embodiments, an improved overburden layer or overburden layer structure is formed over the field region of the substrate to enable the formation of a contact or interconnect structure that has improved characteristics over conventionally formed contacts or interconnect structures.

A semiconductor structure is provided. The semiconductor structure includes an epitaxial structure over a semiconductor substrate. The semiconductor structure also includes a conductive feature over the semiconductor substrate. The conductive feature includes a high-k dielectric layer and a metal layer on the high-k dielectric layer, and a top surface of the metal layer is below a top surface of the high-k dielectric layer. The semiconductor structure further includes a metal-semiconductor compound layer formed on the epitaxial structure. In addition, the semiconductor structure includes a first metal contact structure formed on the top surface of the metal layer of the conductive feature. The semiconductor structure further includes a second metal contact structure formed on the metal-semiconductor compound layer.

Integrated circuit structures including an interconnect feature without a higher-resistance liner material. In absence of a liner, metal of low resistance directly contacts an adjacent dielectric material, enabling lower resistance interconnect. Even for low-k dielectric compositions, adhesion of the metal to the dielectric material is improved through the incorporation of nitrogen proximal to the interface. Prior to deposition of the metal upon a surface of the dielectric, the surface is exposed to nitrogen species to form a nitrogen-rich compound at the surface. The metal deposited upon the surface may then be nitrogen-lean, for example a substantially pure elemental metal or metal alloy.

A method of gap filling a feature on a substrate decreases the feature-to-feature gap fill height variation by using a tungsten halide soak treatment. In some embodiments, the method may include heating a substrate to a temperature of approximately 350 degrees Celsius to approximately 450 degrees Celsius, exposing the substrate to a tungsten halide gas at a process pressure of approximately 5 Torr to approximately 25 Torr, soaking the substrate for a soak time of approximately 5 seconds to approximately 60 seconds with the tungsten halide gas, and performing a metal preclean process and a gap fill deposition on a plurality of features on the substrate after soaking of the substrate has completed.

The present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, portions of an adhesion layer, barrier layer and/or seed layer is protected by a layer of an organic mask material as portions of the adhesion layer, barrier layer and/or seed layer are removed. The layer of organic mask material is modified to improve its resistance to penetration by wet etchants used to remove exposed portions of the adhesion layer, barrier layer and/or seed layer. An example modification includes treating the layer of organic mask material with a surfactant that is absorbed into the layer of organic mask material.

Methods and apparatuses for processing substrates, such as during metal silicide applications, are provided. In one or more embodiments, a method of processing a substrate includes depositing an epitaxial layer on the substrate, depositing a metal silicide seed layer on the epitaxial layer, and exposing the metal silicide seed layer to a nitridation process to produce a metal silicide nitride layer from at least a portion of the metal silicide seed layer. The method also includes depositing a metal silicide bulk layer on the metal silicide nitride layer and forming or depositing a nitride capping layer on the metal silicide bulk layer, where the nitride capping layer contains a metal nitride, a silicon nitride, a metal silicide nitride, or a combination thereof.

Methods of mitigating line bending during feature fill include deposition of an amorphous layer and/or an inhibition treatment during fill.

Methods of forming memory structures are discussed. Specifically, methods of forming 3D NAND devices are discussed. Some embodiments form memory structures with a metal nitride barrier layer, an α-tungsten layer, and a bulk metal material. The barrier layer comprises a TiXN or TaXN material, where X comprises a metal selected from one or more of aluminum (Al), silicon (Si), tungsten (W), lanthanum (La), yttrium (Yt), strontium (Sr), or magnesium (Mg).