A first signal lead pin is bent such that one end is connected to a first signal line of a differential coplanar line, and the other end is apart from a mounting surface. A second signal lead pin is bent such that one end is connected to a second signal line of the differential coplanar line, and the other end is apart from the mounting surface. A ground lead pin is bent such that one end is connected to a ground line of the differential coplanar line, and the other end is apart from the mounting surface.

An object of the present invention is to provide a power semiconductor device capable of improving seismic resistance while suppressing a decrease in assembly efficiency. According to the present invention, a power semiconductor device 1 includes an element installation conductor 2 including a first conductor portion 20a that is made of metal and is used for installing a power semiconductor element 300, a second conductor portion 20b that is made of metal and forms one or more main terminals 2a for transmitting a current to the power semiconductor element 300, and one or more control terminals 2b for transmitting a switching control signal to the power semiconductor element 300, and a third conductor portion 20c that is made of metal and is provided at a tip portion of the control terminal 2b. In the power semiconductor device 1, the element installation conductor 2 is formed so that the thickness of the thickest portion of the second conductor portion 20b is thinner than the thickness of the first conductor portion 20a, and the thickness of the thickest portion of the third conductor portion 20c is thinner than the thickness of the thinnest portion of the second conductor portion 20b.

A packaged electronic device includes a die pad directly connected to a first set of conductive leads of a leadframe structure, a semiconductor die attached to the conductive die pad, a conductive support structure directly connected to a second set of conductive leads, and spaced apart from all other conductive structures of the leadframe structure. A magnetic assembly is attached to the conductive support structure, and a molded package structure that encloses the conductive die pad, the conductive support structure, the semiconductor die, the magnetic assembly and portions of the conductive leads, the molded package structure including a top side, and an opposite bottom side, wherein the lamination structure is centered between the top and bottom sides.

A semiconductor device according to the present embodiment comprises a semiconductor chip comprising a first face and a second face on an opposite side to the first face, and comprising a first electrode in the first face. A first metallic member comprises a first opposed face facing the first electrode and being larger in a profile than the first electrode, the first metallic member comprising a first protruded portion protruded from the first opposed face toward the first electrode and electrically connected to the first electrode. An insulating member coats the semiconductor chip and the first metallic member.

A semiconductor device forming a bidirectional switch includes first and second carriers, first and second semiconductor chips arranged on the first and second carriers, respectively, a first row of terminals arranged along a first side face of the carrier, a second row of terminals arranged along a second side face of the carrier opposite the first side face, and an encapsulation body encapsulating the first and second semiconductor chips. Each row of terminals includes a gate terminal, a sensing terminal and at least one power terminal of the bidirectional switch.

A power module having electrical connection parts, preferably made of metal, each having a main plate, the main plates extending in one and the same main plane so as to be substantially coplanar. At least one of the electrical connection parts includes at least one electrical connector projecting from its main plate. At least one transistor is electrically connected between two upper faces of respectively two of the main plates, and an electrically insulating overmolding, for example made of resin, covers each transistor and at least one portion of the upper faces of the main plates.

A semiconductor package includes a die pad having a die attach surface, a first laterally separated and vertically offset from the die pad, a semiconductor die mounted on the die attach surface and comprising a first terminal on an upper surface of the semiconductor die, an interconnect clip that is electrically connected to the first terminal and to the first lead, and a heat spreader mounted on top of the interconnect clip. The interconnect clip includes a first planar section that interfaces with the upper surface of the semiconductor die and extends past an outer edge side of the die pad. The heat spreader covers an area of the first planar section that is larger than an area of the semiconductor die. The heat spreader laterally extends past a first outer edge side of the die pad that faces the first lead.

According to an aspect of the present disclosure, a semiconductor device includes a substrate, a resin case surrounding a region just above the substrate in a planar view, a semiconductor chip provided in the region and an electrode including a first portion pulled out from an upper surface of the resin case and a second portion provided below the upper surface of the resin case and to be inserted into the resin case, and being electrically connected to the semiconductor chip, wherein a first notch is formed over the first portion to the second portion in the electrode, and a first groove is formed to expose a portion, formed in the second portion, in the first notch on the upper surface of the resin case.

In a described example, an apparatus includes: a package substrate having a die pad configured for receiving a semiconductor die, and having conductive leads spaced from the die pad; a semiconductor die mounted on the die pad, the semiconductor die having bond pads on an active surface configured for making electrical connections; electrical connections coupling the bond pads of the semiconductor die to the conductive leads; mold compound covering a portion of the package substrate, the semiconductor die, and the electrical connections, with the leads extending through the mold compound and having end portions exposed from the mold compound; and the leads having a first portion with a first width and extending with the first width from the mold compound to a second portion having a second width that greater than the first width.

One example described herein includes an integrated circuit (IC) package. The IC package includes a semiconductor die comprising an IC and an IC package enclosure that substantially encloses the semiconductor die. The IC package also includes at least one conductive metal contact. Each of the at least one conductive metal contact is coupled to the semiconductor die and comprises a planar solder surface exterior to the IC package enclosure to which the respective at least one metal contact is soldered to an external conductive metal contact. The planar solder surface includes at least one solder surface feature.