A semiconductor device comprising at least one first gate all around channel having a horizontal physical orientation, wherein the at least one first gate all around channel is comprised of a first material, wherein the at least one first gate all around channel has a sidewall surface with (100) crystal orientation. At least one second gate all around channel having a vertical physical orientation, wherein the second channel is located above the at least one first gate all around channel, wherein the at least one second gate all around channel is comprised of a second material, wherein the at least one second gate all around channel has a sidewall surface with (110) crystal orientation. A gate metal enclosing the at least one first gate all around channel and the at least one second gate all around channel.

The present disclosure describes a method for the formation of gate-all-around nano-sheet FETs with tunable performance. The method includes disposing a first and a second vertical structure with different widths over a substrate, where the first and the second vertical structures have a top portion comprising a multilayer nano-sheet stack with alternating first and second nano-sheet layers. The method also includes disposing a sacrificial gate structure over the top portion of the first and second vertical structures; depositing an isolation layer over the first and second vertical structures so that the isolation layer surrounds a sidewall of the sacrificial gate structure; etching the sacrificial gate structure to expose each multilayer nano-sheet stack from the first and second vertical structures; removing the second nano-sheet layers from each exposed multilayer nano-sheet stack to form suspended first nano-sheet layers; forming a metal gate structure to surround the suspended first nano-sheet layers.

An integrated circuit includes gate-all-around (GAA) nanowire transistors and GAA nanosheet transistors on the same substrate. An array of cells including GAA nanowire transistors and cells including nanosheet transistors are provided. The cells including GAA nanowire transistors can be adjacent cells including GAA nanosheet transistors with isolation structures interposing the cells.

A semiconductor device includes a semiconductor substrate having first and second regions therein, a first lower semiconductor pattern, which protrudes from the semiconductor substrate in the first region and extends in a first direction across the semiconductor substrate, and a first gate electrode, which extends across the first lower semiconductor pattern and the semiconductor substrate in a second direction. A plurality of semiconductor sheet patterns are provided, which are spaced apart from each other in a third direction to thereby define a vertical stack of semiconductor sheet patterns, on the first lower semiconductor pattern. A first gate insulating film is provided, which separates the plurality of semiconductor sheet patterns from the first gate electrode. A second lower semiconductor pattern is provided, which protrudes from the semiconductor substrate in the second region. A plurality of wire patterns are provided, which are spaced apart from each other on the second lower semiconductor pattern. A second gate insulating film is wrapped around each of the plurality of wire patterns.

A field effect transistor includes a source region and a drain region formed within and/or above openings in a dielectric capping mask layer overlying a semiconductor substrate and a gate electrode. A source-side silicide portion and a drain-side silicide portion are self-aligned to the source region and to the drain region, respectively.

A field effect transistor includes a source region and a drain region formed within and/or above openings in a dielectric capping mask layer overlying a semiconductor substrate and a gate electrode. A source-side silicide portion and a drain-side silicide portion are self-aligned to the source region and to the drain region, respectively.

A method includes forming a first transistor including forming a first gate stack, epitaxially growing a first source/drain region on a side of the first gate stack, and performing a first implantation to implant the first source/drain region. The method further includes forming a second transistor including forming a second gate stack, forming a second gate spacer on a sidewall of the second gate stack, epitaxially growing a second source/drain region on a side of the second gate stack, and performing a second implantation to implant the second source/drain region. An inter-layer dielectric is formed to cover the first source/drain region and the second source/drain region. The first implantation is performed before the inter-layer dielectric is formed, and the second implantation is performed after the inter-layer dielectric is formed.

A semiconductor device is provided. The semiconductor device can include a bottom substrate, a device plane over the bottom substrate, a dielectric layer over the device plane, localized substrates over the dielectric layer, and semiconductor devices over the localized substrates. The localized substrates can be separated from each other along a top surface of the bottom substrate. A method of microfabrication is provided. The method can include forming a target layer over a bottom substrate where the target layer includes one or more localized regions that include one or more semiconductor materials. The method can also include performing a thermal process to change crystal structures of the one or more localized regions of the target layer. The method can further include forming semiconductor devices over the localized regions of the target layer.

A semiconductor device having a novel structure is provided. The semiconductor device includes a p-channel transistor and an n-channel transistor provided over a silicon substrate. One of a source and a drain of the p-channel transistor is electrically connected to a first power supply line, one of a source and a drain of the n-channel transistor is electrically connected to a second power supply line, and the other of the source and the drain of the p-channel transistor is connected to the other of the source and the drain of the n-channel transistor. The p-channel transistor includes a first gate electrode and a first back gate electrode provided to face the first gate electrode with a first channel formation region therebetween. The first back gate electrode is formed using a region where an impurity element imparting conductivity is selectively introduced to the silicon substrate. The n-channel transistor is provided above a layer including the p-channel transistor.

An integrated circuit (IC) that includes a memory cell having a first p-type active region, a first n-type active region, a second n-type active region, and a second p-type active region. Each of the first and the second p-type active regions includes a first group of vertically stacked channel layers having a width W1, and each of the first and the second n-type active regions includes a second group of vertically stacked channel layers having a width W2, where W2 is less than W1. The IC structure further includes a standard logic cell having a third n-type fin and a third p-type fin. The third n-type fin includes a third group of vertically stacked channel layers having a width W3, and the third p-type fin includes a fourth group of vertically stacked channel layers having a width W4, where W3 is greater than or equal to W4.