Some embodiments include a memory cell having charge-trapping-material between a semiconductor channel material and a gating region. The charge-trapping-material includes silicon, nitrogen and trap-enhancing-additive. The trap-enhancing-additive includes one or more of carbon, phosphorus, boron and metal. Some embodiments include an integrated assembly having a stack of alternating first and second levels. The first levels include conductive structures and the second levels are insulative. Channel-material-pillars extend through the stack. Charge-trapping-regions are along the channel-material-pillars and are between the channel-material-pillars and the conductive structures. The charge-trapping-regions include a charge-trapping-material which contains silicon, nitrogen and trap-enhancing-additive. The trap-enhancing-additive includes one or more of carbon, phosphorus, boron and metal.

A memory device includes an alternating stack of insulating layers and control gate layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure containing a memory film and a vertical semiconductor channel located within the memory opening. The memory film contains a resonant tunneling barrier stack, a semiconductor barrier layer, and a memory material layer located between the resonant tunneling barrier stack and the semiconductor barrier layer.

A semiconductor device, and method of manufacturing a semiconductor device, includes second conductive patterns separated from each other above a first stack structure which is penetrated by first channel structures and enclosing second channel structures coupled to the first channel structures, respectively. Each of the second conductive patterns includes electrode portions stacked in a first direction and at least one connecting portion extending in the first direction to be coupled to the electrode portions.

Provided are a charge trap evaluation method and semiconductor device including, in an embodiment, a step for applying an initialization voltage that has the same sign as a threshold voltage and is greater than or equal to the threshold voltage between the source electrode 15 and drain electrode 16 of a semiconductor device 1 having an HEMT structure and the substrate 10 of the semiconductor device 1 and initializing a trap state by forcing out trapped charge from a trap level and a step for monitoring the current flowing between the source electrode 15 and drain electrode 16 after the trap state initialization and evaluating at least one from among charge trapping, current collapse, and charge release.

A semiconductor structure includes a substrate, an insulating layer disposed on the substrate, an active layer disposed on the insulating layer, a first semiconductor device formed in a first device region of the active layer, a charge trap structure through the active layer and surrounding the first device region, and a charge trap layer between the insulating layer and the substrate and extending laterally to underlie the first device region and the charge trap structure.

Semiconductor devices and methods of manufacturing the same are provided. The semiconductor devices may have a non-volatile memory (NVM) transistor including a charge-trapping layer and a blocking dielectric, a field-effect transistor (FET) of a first type including a first gate dielectric having a first thickness, a FET of a second type including a second gate dielectric having a second thickness, and a FET of a third type including a third gate dielectric having a third thickness. In some embodiments, the first, second, and third gate dielectric includes a high dielectric constant (high-K) dielectric layer, and the first thickness is greater than the second thickness, the second thickness is greater than the third thickness. Other embodiments are also described.

A semiconductor integrated circuit device may include a structure, a first capping layer, a channel layer and a second capping layer. The structure may have an opening formed in the structure. The first capping layer may be formed in the opening of the structure. The channel layer may be arranged between the structure and the first capping layer. The second capping layer may be arranged on the channel layer and the first capping layer.

A 3-dimensional flash memory device and methods of fabricating and driving the same are provided. The device includes: a channel layer extending over a substrate in a first direction perpendicular to a surface of the substrate; an information storing layer extending along a sidewall of the channel layer in the first direction; control gates each surrounding the channel layer, with the information storing layer between the channel layer and the control gates; an insulating layer being between the control gates in the first direction and separating the control gates from each other; a fixed charge region disposed at an interface of the insulating layer and the information storing layer or in a portion of the information storing layer between the control gates in the first direction; and a doped region induced by the fixed charge region and disposed at a surface of the channel layer facing the fixed charge region.

A memory cell of a charge-trapping non-volatile memory includes a semiconductor substrate, a well region, a first doped region, a second doped region, a gate structure, a protecting layer, a charge trapping layer, a dielectric layer, a first conducting line and a second conducting line. The first doped region and the second doped region are formed under a surface of the well region. The gate structure is formed over the surface of the well region. The protecting layer formed on the surface of the well region. The charge trapping layer covers the surface of the well region, the gate structure and the protecting layer. The dielectric layer covers the charge trapping layer. The first conducting line is connected with the first doped region. The second conducting line is connected with the second doped region.

In one embodiment, the semiconductor device includes a substrate having an impurity region, and the substrate and the impurity region have a different impurity characteristic. The semiconductor device further includes a stack of alternating first interlayer insulating layers and gate electrode layers on the substrate; at least one second interlayer insulating layer formed on the stack; a plurality of bit lines formed on the second interlayer insulating layer; and a first plurality of channel structures formed through the stack on the substrate. The first plurality of channel structures are electrically connected to respective ones of the plurality of bit lines. A second plurality of channel structures are formed through the stack on the impurity region, and the second plurality of channel structures are electrically insulated from the plurality of bit lines.