A method of forming a fin field effect transistor (finFET), including forming a temporary gate structure having a sacrificial gate layer and a dummy gate layer on the sacrificial gate layer, forming a gate spacer layer on each sidewall of the temporary gate structure, forming a source/drain spacer layer on the outward-facing sidewall of each gate spacer layer, removing the dummy gate layer to expose the sacrificial gate layer, removing the sacrificial gate layer to form a plurality of recessed cavities, and forming a gate structure, where the gate structure occupies at least a portion of the plurality of recessed cavities.

A semiconductor device including: a semiconductor substrate including an active region; a plurality of conductive structures formed over the semiconductor substrate; an isolation layer filling a space between the conductive structures and having an opening that exposes the active region between the conductive structures; a pad formed in a bottom portion of the opening and in contact with the active region; a plug liner formed conformally over a sidewall of the opening and exposing the pad; and a contact plug formed over the pad inside the opening.

A field effect transistor (FET) including a substrate, a plurality of semiconductor epitaxial layers deposited on the substrate, and a heavily doped gate layer deposited on the semiconductor layers. The FET also includes a plurality of castellation structures formed on the heavily doped gate layer and being spaced apart from each other, where each castellation structure includes at least one channel layer. A gate metal is deposited on the castellation structures and between the castellation structures to be in direct electrical contact with the heavily doped gate layer. A voltage potential applied to the gate metal structure modulates the at least one channel layer in each castellation structure from an upper, lower and side direction.

A semiconductor device is provided and includes a semiconductor fin protruding from a semiconductor substrate. The semiconductor fin includes plural pairs of semiconductor layers on the semiconductor substrate, each pair of semiconductor layers consists of a first semiconductor layer of a first conductivity type, and a second semiconductor layer of a second conductivity type. The second semiconductor layer is stacked on and contacts the first semiconductor layer.

In an embodiment, a transistor device a semiconductor substrate having a main surface, and a cell field including a plurality of transistor cells of a power transistor. The cell field further includes: a body region of a second conductivity type; a source region of a first conductivity type on or in the body region, the first conductivity type opposing the second conductivity type; a gate trench in the main surface of the semiconductor substrate; a gate dielectric lining the gate trench; a metal gate electrode arranged in the gate trench on the gate dielectric; and an electrically insulating cap arranged on the metal gate electrode. A method of fabricating a gate of the transistor device is also described.

A device includes a substrate, a shallow trench isolation (STI) structure, an isolation structure, and a gate stack. The substrate has a semiconductor fin. The shallow trench isolation (STI) structure is over the substrate and laterally surrounding the semiconductor fin. The isolation structure is disposed on a top surface of the STI structure. The gate stack crosses the semiconductor fin, over the STI structure, and in contact with a sidewall the isolation structure, in which the gate stack includes a high-k dielectric layer extending from a sidewall of the semiconductor fin to the top surface of the STI structure and terminating prior to reaching the sidewall of the isolation structure, and the high-k dielectric layer is in contact with the top surface of the STI structure. The gate stack includes a gate electrode over the high-k dielectric layer and in contact with the sidewall of the isolation structure.

A monolithically integrated bidirectional switch includes: an output terminal; a control terminal; a compound semiconductor substrate; a common drift region in the compound semiconductor substrate and in series between the input terminal and the output terminal; a first gate; and a second gate. The first gate is electrically connected to the control terminal and the second gate is electrically connected to the input terminal, or one of the first gate and the second gate is a normally-on gate and the other one of the first gate and the second gate is a normally-off gate. In either case, the monolithically integrated bidirectional switch is configured to conduct current in a single direction from the input terminal to the output terminal through the common drift region. A corresponding power electronic system that uses the monolithically integrated bidirectional switch is also described.

A transistor display panel including: a substrate; a gate electrode disposed on the substrate; a semiconductor that overlaps the gate electrode; an upper electrode disposed on the semiconductor; a source connection member and a drain connection member disposed on the same layer as the upper electrode and respectively connected with the semiconductor; a source electrode connected with the source connection member and the upper electrode; and a drain electrode connected with the drain connection member.

A display device is disclosed, which includes: a first substrate; an oxide semiconductor layer disposed on the first substrate; a silicon semiconductor layer disposed on the first substrate; and a capacitor including a first conductive component and a second conductive component, wherein the first conductive component is electrically connected to the oxide semiconductor layer and the second conductive component is electrically connected to the silicon semiconductor layer.

Disclosed herein are IC structures, packages, and device assemblies with III-N transistors that include additional materials, referred to herein as “stressor materials,” which may be selectively provided over portions of polarization materials to locally increase or decrease the strain in the polarization material. Providing a compressive stressor material may decrease the tensile stress imposed by the polarization material on the underlying portion of the III-N semiconductor material, thereby decreasing the two-dimensional electron gas (2DEG) and increasing a threshold voltage of a transistor. On the other hand, providing a tensile stressor material may increase the tensile stress imposed by the polarization material, thereby increasing the 2DEG and decreasing the threshold voltage. Providing suitable stressor materials enables easier and more accurate control of threshold voltage compared to only relying on polarization material recess.