A method of fabricating a metal gate structure in a semiconductor device is disclosed. The method comprises removing a dummy poly gate, removing IL oxide and STI using a dry etch process and a wet lateral etch process to form a T-shape void in the semiconductor device, and depositing metal gate material in the T-shape void to form a T-shape structure in a metal gate line-end. A semiconductor device fabricated from a process that included the removal of a dummy poly gate is disclosed. The semiconductor device comprises an OD fin and a metal gate fabricated above a section of the OD fin and adjacent to a side section of the OD fin. The metal gate has a T-shape structure in a metal gate line-end. The T-shape structure was formed by removing IL oxide and STI using a dry and a wet lateral etch process to form a T-shape void.

A method for producing a semiconductor device includes a first step of forming a fin-shaped semiconductor layer on a semiconductor substrate and forming a first insulating film; a second step of forming a pillar-shaped semiconductor layer and a first dummy gate; a third step of forming a second dummy gate; a fourth step of forming a fifth insulating film and a sixth insulating film; a fifth step of depositing a first interlayer insulating film, removing the second dummy gate and the first dummy gate, forming a gate insulating film, depositing metal, and performing etch back to form a gate electrode and a gate line; a seventh step of forming a seventh insulating film; and an eighth step of forming insulating film sidewalls, forming a first epitaxially grown layer on the fin-shaped semiconductor layer, and forming a second epitaxially grown layer on the pillar-shaped semiconductor layer.

The present invention provides a vertical-type thin film transistor (TFT) and methods of fabricating vertical TFTs. The vertical TFT may comprise a source electrode and a drain electrode, the drain electrode and the source electrode being positioned on vertically separated planes. A semiconductor layer may be arranged in between the source electrode and the drain electrode. At least one gate electrode may be embedded in the semiconductor layer. At least one of the source electrode and the drain electrode comprise patterned electrodes. One or all of the gate electrodes, the source electrode and the drain electrode may be patterned electrodes. The patterned electrodes may comprise one or more of fingers or combs, micro perforations, a mesh structure, or a lattice structure. Back side exposed fabrication techniques may be used to fabricate various of the vertical TFT embodiments.

A multi-channel semiconductor-on-insulator (SOI) transistor includes a substrate having an electrically insulating layer thereon and a semiconductor active layer on the electrically insulating layer. A vertical stack of spaced-apart insulated gate electrodes, which are buried within the semiconductor active layer, is also provided. This vertical stack includes a first insulated gate electrode extending adjacent the electrically insulating layer and an (N−1)th insulated gate electrode that is spaced from a surface of the semiconductor active layer, where N is a positive integer greater than two. An Nth insulated gate electrode is provided on the surface of the semiconductor active layer. A pair of source/drain regions are provided within the semiconductor active layer. These source/drain regions extend adjacent opposing sides of the vertical stack of spaced-apart insulated gate electrodes. In some of these aspects, the semiconductor active layer extends between the pair of source/drain regions and the electrically insulating layer, whereas the first insulated gate electrode contacts the electrically insulating layer.

A semiconductor transistor device includes a substrate having an active area and a trench isolation region surrounding the active area, a gate oxide layer, a gate, a spacer on a sidewall of the gate, a doping region on one side of the gate, an insulating cap layer covering the gate, the spacer and the doping region, and a redistributed contact layer (RCL) on the insulating cap layer. The RCL extends from the active area to the trench isolation region. A contact plug is disposed above the trench isolation region and is electrically connected to the gate or the doping region through the RCL.

An integrated electronic detector operates to detecting a variation in potential on an input terminal. The detector includes a MOS transistor having a drain forming an output. Variation in drain current is representative of the variation in potential. A bipolar transistor has a base forming the input terminal and a collector electrically connected to the gate of the MOS transistor. The detector has a first configuration in which the bipolar transistor is conducting and the MOS transistor is turned off. The detector has a second configuration in which the bipolar transistor is turned off and the MOS transistor is in a sub-threshold operation. Transition of the detector from the first configuration to the second configuration occurs in response to the variation in potential.

A semiconductor device includes a first active structure on a substrate including a first epitaxial pattern, a second epitaxial pattern and a first channel pattern between the first epitaxial pattern and the second epitaxial pattern, the first channel pattern including at least one channel pattern stacked on the substrate. A first gate structure is disposed on top and bottom surfaces of the first channel pattern. A second active structure on the substrate and includes the second epitaxial pattern, a third epitaxial pattern and a second channel pattern between the second epitaxial pattern and the third epitaxial pattern in the first direction. The second channel pattern includes at least one channel pattern stacked on the substrate. The number of stacked second channel patterns is greater than the number of stacked first channel patterns. A second gate structure is disposed on top and bottom surfaces of the second channel pattern.

A semiconductor device includes a first oxide insulating layer over a first insulating layer, an oxide semiconductor layer over the first oxide insulating layer, a source electrode layer and a drain electrode layer over the oxide semiconductor layer, a second insulating layer over the source electrode layer and the drain electrode layer, a second oxide insulating layer over the oxide semiconductor layer, a gate insulating layer over the second oxide insulating layer, a gate electrode layer over the gate insulating layer, and a third insulating layer over the second insulating layer, the second oxide insulating layer, the gate insulating layer, and the gate electrode layer. A side surface portion of the second insulating layer is in contact with the second oxide insulating layer. The gate electrode layer includes a first region and a second region. The first region has a width larger than that of the second region.

A method for manufacturing a thin film transistor substrate, the method can include a first mask process for forming a gate electrode on a substrate; a step for forming a gate insulating layer covering the gate electrode; a second mask process for forming a source electrode overlapping with one side of the gate electrode, and a drain electrode overlapping with other side of the gate electrode and being apart from the source electrode, on the gate insulating layer; and a third mask process for forming an oxide semiconductor layer extending from the source electrode to the drain electrode, and an etch stopper having the same shape and size with the oxide semiconductor layer on the oxide semiconductor layer.

In a method of manufacturing a thin film transistor substrate, a first metal layer is formed on a first surface of a base substrate. The base substrate is cooled by contacting the first metal layer with a first cooling plate and by contacting a second surface of the base substrate with a second cooling plate. The first and second surfaces of the base substrate face opposite directions. A gate electrode is formed by patterning the first metal layer. A source electrode and a drain electrode are formed. The source electrode is spaced apart from the drain electrode. The source and drain electrodes partially overlap the gate electrode. A pixel electrode electrically connected to the drain electrode is formed.