A MOSFET device includes a semiconductor substrate, serving as a drain region, and an epitaxial region disposed on an upper surface of the substrate. The MOSFET device includes multiple body regions formed in the epitaxial region, and multiple source regions. The body regions are disposed near an upper surface of the epitaxial region and spaced laterally from one another, and each of the source regions is disposed in a corresponding one of the body regions near an upper surface of the body region. The MOSFET device includes a gate structure having multiple planar gates and a trench gate. Each of the planar gates is disposed on the upper surface of the epitaxial region overlapping a corresponding body region. The trench gate is formed partially through the epitaxial region and between the body regions, an upper surface of the trench gate being recessed below the upper surface of the epitaxial region.

Semiconductor device structures and methods for manufacturing the same are provided. The semiconductor device structure includes a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a barrier layer, a third nitride semiconductor layer and a gate structure. The first nitride semiconductor layer is disposed on the substrate. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer and has a bandgap greater than that of the first nitride semiconductor layer. The barrier layer is disposed on the second nitride semiconductor layer and has a bandgap greater than that of the second nitride semiconductor layer. The third nitride semiconductor layer is doped with impurity and disposed on the barrier layer. The gate structure is disposed on the third nitride semiconductor layer.

Some embodiments include a semiconductor construction having a gate extending into a semiconductor base. Conductively-doped source and drain regions are within the base adjacent the gate. A gate dielectric has a first segment between the source region and the gate, a second segment between the drain region and the gate, and a third segment between the first and second segments. At least a portion of the gate dielectric comprises ferroelectric material. In some embodiments the ferroelectric material is within each of the first, second and third segments. In some embodiments, the ferroelectric material is within the first segment or the third segment. In some embodiments, a transistor has a gate, a source region and a drain region; and has a channel region between the source and drain regions. The transistor has a gate dielectric which contains ferroelectric material between the source region and the gate.

The present disclosure provides a method of forming a semiconductor device including an nFET structure and a pFET structure where each of the nFET and pFET structures include a semiconductor substrate and a gate trench. The method includes depositing an interfacial layer in each gate trench; depositing a first metal oxide layer over the interfacial layer; removing the first metal oxide layer from the pFET structure; depositing a ferroelectric layer in each gate trench; depositing a second metal oxide layer over the ferroelectric layer; removing the second metal oxide layer from the nFET structure; and depositing a gate electrode in each gate trench.

Provided is a semiconductor device which use a two-dimensional semiconductor material as a channel layer. The semiconductor device includes: a gate electrode on a substrate; a gate dielectric on the gate electrode; a channel layer on the gate dielectric; and a source electrode and a drain electrode that may be electrically connected to the channel layer. The gate dielectric has a shape with a height greater than a width, and the channel layer includes a two-dimensional semiconductor material.

Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method comprises forming a first stack structure and a second stack structure in a first area over a substrate, wherein each of the stack structures includes semiconductor layers separated and stacked up; depositing a first interfacial layer around each of the semiconductor layers of the stack structures; depositing a gate dielectric layer around the first interfacial layer; forming a dipole oxide layer around the gate dielectric layer; removing the dipole oxide layer around the gate dielectric layer of the second stack structure; performing an annealing process to form a dipole gate dielectric layer for the first stack structure and a non-dipole gate dielectric layer for the second stack structure; and depositing a first gate electrode around the dipole gate dielectric layer of the first stack structure and the non-dipole gate dielectric layer of the second stack structure.

According to one embodiment, a transistor includes a gate electrode, an oxide semiconductor layer which overlaps the gate electrode and including a central portion and an end portion, and a source electrode and a drain electrode each connected to the oxide semiconductor layer, wherein an oxidation degree of the end portion is lower than an oxidation degree of the central portion, and a length of the gate electrode overlapping the central portion is greater than a length of the gate electrode overlapping the end portion.

A semiconductor device may include a first device on a first portion of a substrate, a second device on a second portion of the substrate, and a third device on a third portion of the substrate. The third device may include an oxide layer that is formed from an oxide layer that is a sacrificial oxide layer for the first device and the second device. The third device may include a gate provided on the oxide layer, a set of spacers provided on opposite sides of the gate, and a source region provided in the third portion of the substrate on one side of the gate. The third device may include a drain region provided in the third portion of the substrate on another side of the gate, and a protective oxide layer provided on a portion of the gate and a portion of the drain region.

A first field effect transistor contains a first active region including a source region, a drain region and a channel region located between the source region and the drain region, a first gate dielectric overlying the active region, and a first gate electrode overlying the first gate dielectric. A second field effect transistor contains a second active region including a source region, a drain region and a channel region located between the source region and the drain region, a second gate dielectric overlying the active region, a second gate electrode overlying the second gate dielectric. A trench isolation region surrounds the first and the second active regions. The first field effect transistor includes a fringe region in which the first gate electrode extends past the active region perpendicular to the source region to drain region direction and the second field effect transistor does not include the fringe region.

Provided is a field effect transistor including a gate insulating layer having a two-dimensional material. The field effect transistor may include a first channel layer; a second channel layer disposed on the first channel layer; a gate insulating layer disposed on the second channel layer; a gate electrode disposed on the gate insulating layer; a first electrode electrically connected to the first channel layer; and a second electrode electrically connected to the second channel layer. Here, the gate insulating layer may include an insulative, high-k, two-dimensional material.