Patent classifications
H01L29/42384
DISPLAY DEVICE
The purpose of the invention is suppressing a kink phenomenon and improvoning the image quality of a display device. The display device has a TFT in a pixel. The TFT has a semiconductor layer, a first insulating layer under the semiconductor layer, a second insulating layer over the semiconductor layer, and a gate electrode facing the semiconductor layer with a gap. The gate electrode has a first gate electrode portion facing a lower surface of the semiconductor layer, a second gate electrode portion facing an upper surface of the semiconductor layer, and a third gate electrode portion facing a lateral surface of the semiconductor layer and connected to the first and second gate electrode portions. A laminated part where the first and second insulating layers are stacked is around the semiconductor layer, and a part of the laminated part is between the lateral surface and the third gate electrode portion.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A minute transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A transistor having a high on-state current is provided. A semiconductor device including the transistor is provided. A semiconductor device having a high degree of integration is provided. A semiconductor device including an oxide semiconductor; a second insulator; a second conductor; a third conductor; a fourth conductor; a fifth conductor; a first conductor and a first insulator embedded in an opening portion formed in the second insulator, the second conductor, the third conductor, the fourth conductor, and the fifth conductor; a region where a side surface and a bottom surface of the second conductor are in contact with the fourth conductor; and a region where a side surface and a bottom surface of the third conductor are in contact with the fifth conductor.
SPUTTERING TARGET AND METHOD FOR MANUFACTURING THE SAME
A novel metal oxide or a novel sputtering target is provided. A sputtering target includes a conductive material and an insulating material. The insulating material includes an oxide, a nitride, or an oxynitride including an element M1. The element M1 is one or more kinds of elements selected from Al, Ga, Si, Mg, Zr, Be, and B. The conductive material includes an oxide, a nitride, or an oxynitride including indium and zinc. A metal oxide film is deposited using the sputtering target in which the conductive material and the insulating material are separated from each other.
Semiconductor device and method for manufacturing the same
It is an object to provide a highly reliable semiconductor device including a thin film transistor with stable electric characteristics. In a semiconductor device including an inverted staggered thin film transistor whose semiconductor layer is an oxide semiconductor layer, a buffer layer is provided over the oxide semiconductor layer. The buffer layer is in contact with a channel formation region of the semiconductor layer and source and drain electrode layers. A film of the buffer layer has resistance distribution. A region provided over the channel formation region of the semiconductor layer has lower electrical conductivity than the channel formation region of the semiconductor layer, and a region in contact with the source and drain electrode layers has higher electrical conductivity than the channel formation region of the semiconductor layer.
Semiconductor device including flip-flop circuit which includes transistors
As a display device has a higher definition, the number of pixels, gate lines, and signal lines are increased. When the number of the gate lines and the signal lines are increased, a problem of high manufacturing cost, because it is difficult to mount an IC chip including a driver circuit for driving of the gate and signal lines by bonding or the like. A pixel portion and a driver circuit for driving the pixel portion are provided over the same substrate, and at least part of the driver circuit includes a thin film transistor using an oxide semiconductor interposed between gate electrodes provided above and below the oxide semiconductor. Therefore, when the pixel portion and the driver portion are provided over the same substrate, manufacturing cost can be reduced.
Multi-functional field effect transistor with intrinsic self-healing properties
The present invention provides a self-healing field-effect transistor (FET) device comprising a self-healing substrate and a self-healing dielectric layer, said substrate and said layer comprising a disulfide-containing poly(urea-urethane) (PUU) polymer, wherein the dielectric layer has a thickness of less than about 10 μm, a gate electrode, at least one source electrode, and at least one drain electrode, said electrodes comprising electrically conductive elongated nanostructures; and at least one channel comprising semi-conducting elongated nanostructures. Further provided is a method for fabricating the FET device.
Transistor array substrate and electronic device including same
Provided are a transistor array substrate and an electronic device. A first active layer includes a first area, a second area spaced apart from the first area, and a channel area provided between the first area and the second area. A gate insulating film is disposed on the first active layer. A gate electrode is disposed on the gate insulating film to overlap a portion of the channel area of the first active layer. The gate electrode overlaps a portion of at least one area of the first and second areas of the first active layer. Deteriorations in the channel area are prevented.
ARRAY SUBSTRATE, DISPLAY PANEL, DISPLAY APPARATUS, AND METHOD FOR MANUFACTURING ARRAY SUBSTRATE
Provided are an array substrate, a display panel, a display apparatus and a method for manufacturing an array substrate. The array substrate includes: a base substrate; an active layer, which is located on one side of the base substrate, where the active layer includes a channel region, a conductive source region, which is located on one side of the channel region, and a conductive drain region, which is located on the other side of the channel region; and a metal layer, which is located on the side of the active layer that is away from the base substrate, where the metal layer includes a gate electrode and a signal line, which are arranged on the same layer, and the thickness of the gate electrode perpendicular to the base substrate is less than the thickness of the signal line perpendicular to the base substrate.
RADIO FREQUENCY DEVICES WITH PHOTO-IMAGEABLE POLYMERS AND RELATED METHODS
RF devices, and more particularly RF devices with photo-imageable polymers for high frequency enhancements and related methods are disclosed. High frequency enhancements are realized by providing air cavities registered with one or more operating portions of RF devices. The air cavities are formed by photo-imageable polymer structures that provide separation from high dielectric constant materials associated with sealing materials, such as overmold materials, that are typically used for environmental and/or mechanical protection in RF devices. Related methods are disclosed that include forming the photo-imageable polymer structures and corresponding air cavities through various lamination and patterning of photo-imageable polymer layers. Further radiation hardening steps are disclosed that may be applied to the photo-imageable polymer structures after air cavities are formed to promote improved structural integrity of the air cavities during subsequent fabrication steps and during operation of the RF devices.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes a semiconductor substrate, a first semiconductor stack, a second semiconductor stack, a first gate structure, and a second gate structure. The semiconductor substrate comprising a first device region and a second device region. The first semiconductor stack is located on the semiconductor substrate over the first device region, and has first channels. The second semiconductor stack is located on the semiconductor substrate over the second device region, and has second channels. A total number of the first channels is greater than a total number of the second channels. The first gate structure encloses the first semiconductor stack. The second gate structure encloses the second semiconductor stack.