Provided is a semiconductor device including; at least a semiconductor layer; and a gate electrode that is arranged directly or via another layer on the semiconductor layer, the semiconductor device being configured in such a manner as to cause a current to flow in the semiconductor layer at least in a first direction that is along with an interface between the semiconductor layer and the gate electrode, the semiconductor layer having a corundum structure, a direction of a c-axis in the semiconductor layer being the first direction.

A semiconductor device includes a semiconductor substrate in which a first region having a freewheeling diode arranged therein, second regions having an IGBT arranged therein, and a withstand-voltage retention region surrounding the first region and the second regions in plan view are defined. The semiconductor substrate has a first main surface and a second main surface. The semiconductor substrate includes an anode layer having a first conductivity type, which is arranged in the first main surface of the first region, and a diffusion layer having the first conductivity type, which is arranged in the first main surface of the withstand-voltage retention region adjacently to the anode layer. A first trench is arranged in the first main surface on a side of the anode layer with respect to a boundary between the anode layer and the diffusion layer.

Provided in the present disclosure are an IGBT device backside structure and a preparation method therefor, and an IGBT device, the IGBT device backside structure comprising a buffer layer, the buffer layer comprising a first activation efficiency buffer area corresponding to an active area of the IGBT device and a second activation efficiency buffer area corresponding to a terminal area of the IGBT device, the activation efficiency of the first activation efficiency buffer area being less than the activation efficiency of the second activation efficiency buffer area.

According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, a first semiconductor layer, a second semiconductor layer, and a first insulating layer. A position of the third electrode in a first direction is between a position of the first electrode in the first direction and a position of the second electrode in the first direction. The first semiconductor layer includes Al.sub.x1Ga.sub.1-x1N and includes a first partial region, a second partial region, and a third partial region. The second semiconductor layer includes Al.sub.x2Ga.sub.1-x2N. A portion of the second semiconductor layer is between the third partial region and the third electrode in the second direction. The first insulating layer includes a first insulating region. The first insulating region is between the third electrode and the portion of the second semiconductor layer in the second direction.

A power semiconductor device includes a semiconductor body and a first terminal at the semiconductor body. The first terminal has a first side for adjoining an encapsulation and a second side for adjoining the semiconductor body. The first terminal includes, at the first side, a top layer; and, at the second side, a base layer coupled with the top layer, wherein a sidewall of the top layer and/or a sidewall of the base layer is arranged in an angle smaller than 85° with respect to a plane.

Provided is a semiconductor package modularized and manufactured by preparing a main block for putting on a semiconductor chip, an insulator, and one or more sub block, preparing the semiconductor chip, preparing an adhesive used in attaching the semiconductor chip, attaching the semiconductor chip to an upper surface or upper and lower surfaces of the main block, performing an electrical connection of the semiconductor chip, preparing a substrate comprising a pattern enabling an electrical connection and vertically attaching one side of the main block to the pattern of the substrate to enable an electrical connection. In the semiconductor package above, an accumulation rate increases on the substrate due to a vertically arranged structure of the semiconductor chips and a heat emission area is enlarged to improve a heat emission effect.

A semiconductor device of embodiments includes: a silicon carbide layer having a first face having an off angle equal to or more than 0° and equal to or less than 8° with respect to a {0001} face and a second face facing the first face and having a 4H-SiC crystal structure; a gate electrode extending in a first direction parallel to the first face; a silicon oxide layer between the silicon carbide layer and the gate electrode; and a region disposed between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration equal to or more than 1 × 10.sup.21 cm.sup.-3. Assuming that a first reference length in the first direction is 0.5 .Math.m, a surface roughness of a surface of the silicon carbide layer in a range of the first reference length is equal to or less than 1 nm.

A semiconductor device comprises a semiconductor die having a first region and a second region, wherein an operating temperature of the second region is lower than an operating temperature of the first region. A plurality of first tubs are respectively disposed in the first region, the second region, or both. The semiconductor device further comprises a power device comprising a plurality of power device cells, and a diode having a plurality of diode cells. The power devices cells are disposed within tubs or portions of tubs that are in the first region, and the diode cells are disposed within tubs or portions of tubs that are in the second region. The power device may comprise a vertical metal oxide semiconductor field effect transistor (MOSFET), and the diode may comprise a vertical Schottky barrier diode (SBD).

A semiconductor device includes a semiconductor substrate having a major surface and both an element-forming region and an outer peripheral voltage-withstanding region that are provided on the major surface side of the semiconductor substrate. The element-forming region includes both a cell region for forming a power element and a circuit element region for forming at least one circuit element. The circuit element region is interposed between the outer peripheral voltage-withstanding region and the cell region. The outer peripheral voltage-withstanding region includes a boundary region that adjoins the element-forming region. In the boundary region, there is provided one or more voltage-withstanding regions. At least one of the one or more voltage-withstanding regions has a withstand voltage lower than both the withstand voltages of the cell region and the circuit element region.

An insulated gate bipolar transistor and a fabrication method therefor, wherein the fabrication method for the insulated gate bipolar transistor comprises the following steps: implanting hydrogen ions, arsenic ions, or nitrogen ions into a substrate from a back surface of the insulated gate bipolar transistor so as to form an n-type heavily doped layer (202) of a reverse conduction diode, the reverse conduction diode being a reverse conduction diode built into the insulated gate bipolar transistor. The described fabrication method and the obtained insulated gate bipolar transistor from a recombination center in an n+ junction of the reverse conduction diode, thereby accelerating the reverse recovery speed of the built-in reverse conduction diode, shortening the reverse recovery time thereof, and improving the performance of the insulated gate bipolar transistor.