Disclosed are a laterally diffused metal oxide semiconductor device and a method for preparing the same. The device includes a substrate (101) of a first conductivity type, a drift region (102) of a second conductivity type, a longitudinal floating field plate array and a plurality of implantation regions (103) of the first conductivity type. The drift region is located in the substrate of the first conductivity type. The longitudinal floating field plate array includes a plurality of longitudinal floating field plate structures (104) arranged at intervals in rows and columns. Each longitudinal floating field plate structures includes a dielectric layer (1041) disposed on an inner surface of a trench and a conductive layer (1042) filling the trench. The plurality of implantation regions are located in the drift region of, each implantation region is located between two adjacent longitudinal floating field plate structures in each row.

A semiconductor structure including a substrate, a first well, a second well, a first doped region, a second doped region, a gate electrode, an insulating layer, a field plate, and a tunable circuit is provided. The first and second wells are formed on the substrate. The first doped region is formed in the first well. The second doped region is formed in the second well. The gate electrode is disposed over the substrate. The gate electrode, the first doped region, and the second doped region constitute a transistor. The insulating layer is disposed on the substrate and overlaps the gate electrode. The field plate overlaps the insulating layer and the gate electrode. The tunable circuit provides either a first short-circuit path between the field plate and the gate electrode, or a second short-circuit path between the field plate and the first doped region.

A transistor structure includes a gate, a spacer, a channel region, a first concave, and a first conductive region. The gate is above a silicon surface. The spacer is above the silicon surface and at least covers a sidewall of the gate. The channel region is under the silicon surface. The first conductive region is at least partially formed in the first concave, wherein a conductive region of a neighborhood transistor structure next to the transistor structure is at least partially formed in the first concave.

Provided is a semiconductor device including a semiconductor chip which has a main surface, a high potential region which is formed in a surface layer portion of the main surface, a low potential region which is formed in the surface layer portion of the main surface at an interval from the high potential region, a first conductive type drift region which is formed in a region between the high potential region and the low potential region in the surface layer portion of the main surface, and a first conductive type resurf region which is formed partially in a surface layer portion of the drift region such as to expose a part of a region which serves as a current path in the drift region from the main surface and which has an impurity concentration higher than that of the drift region.

A semiconductor device includes a semiconductor substrate of a first conductivity type, a body region of the first conductivity type, a source region of a second conductivity type, a drain region of the second conductivity type, a gate electrode, a drift region of the second conductivity type, an implanted oxide layer, and a semiconductor region of the first conductivity type. The semiconductor region is formed to extend in a direction along the top face of the semiconductor substrate. A first distance and a second distance are set so that an intensity of 0.35 MV/cm or less is observed in an electric field of a first region including the end portion of the drift region and in an electric field of a second region between the end of the semiconductor region and the drain region.

The Rds*Cgd figure of merit (FOM) of a laterally diffused metal oxide semiconductor (LDMOS) transistor is improved by forming the drain drift region with a number of dopant implants at a number of depths, and forming a step-shaped back gate region with a number of dopant implants at a number of depths to adjoin the drain drift region.

A laterally-diffused metal-oxide semiconductor, “LDMOS”, device and a method of making the same. The device includes a gate located on a major surface of a semiconductor die, a source region located in the die on a first side of the gate, a drain drift region located in the die on a second side of the gate opposite the first side, a first spacer located adjacent to a first sidewall of the gate on the first side of the gate, and a second spacer located adjacent to a second sidewall of the gate on the second side of the gate. The second spacer is located between the gate and the drain drift region. The second spacer comprises a proximal spacer portion and a distal spacer portion. The proximal spacer portion is located between the gate and the distal spacer portion. The proximal spacer portion and the distal spacer portion define a recess.

A method for manufacturing a semiconductor device includes forming a plate structure over an isolation region. A drain electrode electrically connected to a drift region underlying the isolation region is formed, wherein the drain electrode is separated from a first location of the plate structure by a first distance along a central axis of an active area of the semiconductor device in a direction of a current flow between a source and a drain of the semiconductor device, the drain electrode is separated from a second location of the plate structure by a second distance along a line parallel to the central axis and within the active area. The first distance is less than the second distance.

A semiconductor device includes a drain region and a source region disposed on a substrate, a gate insulating layer, a gate electrode, a silicide barrier, a source contact plug, a drain contact plug, and a field plate plug. The gate insulating layer, disposed between the drain region and the source region, includes a first gate insulating layer having a first thickness and a second gate insulating layer having a second thickness larger than the first thickness. A bottom surface of the first gate insulating layer and a bottom surface of the second gate insulating layer are parallel to each other. The gate electrode is disposed on the first and second gate insulating layers. The silicide barrier layer is disposed in contact with a top surface of the second gate insulating layer and a top surface of the gate electrode. The source contact plug is connected to the source region.

A semiconductor structure is disclosed. The semiconductor structure includes: a substrate of a first conductivity; a first region of the first conductivity formed in the substrate; a second region of the first conductivity formed in the first region, wherein the second region has a higher doping density than the first region; a source region of a second conductivity formed in the second region; a drain region of the second conductivity formed in the substrate; a pickup region of the first conductivity formed in the second region and adjacent to the source region; and a resist protective oxide (RPO) layer formed on a top surface of the second region. An associated fabricating method is also disclosed.