An electronic device including a two-dimensional material is provided. The electronic device may include a substrate; a metal layer on a partial region of the substrate; a two-dimensional material layer over the metal layer and an upper surface of the substrate; and an insertion layer between the metal layer and the two-dimensional material layer.

A transistor based on topological insulators is provided. In an embodiment a topological insulator is used to form both the channel as well as the source/drain regions, wherein the channel has a first thickness such that the topological insulator material has properties of a semiconductor material and the source/drain regions have a second thickness such that the topological insulator has properties of a conductive material.

Provided is a method for growing a nanowire, including: providing a substrate with a base portion having a first surface and at least one support structure extending above or below the first surface; forming a dielectric coating on the at least one support structure; forming a photoresist coating over the substrate; forming a metal coating over at least a portion of the dielectric coating; removing a portion of the dielectric coating to expose a surface of the at least one support structure; removing a portion of the at least one support structure to form a nanowire growth surface; growing at least one nanowire on the nanowire growth surface of a corresponding one of the at least one support structure, wherein the nanowire comprises a root end attached to the growth surface and an opposing, free end extending from the root end; and elastically bending the at least one nanowire.

A reinforced thin-film device (100, 200, 500) including a substrate (101) having a top surface for supporting an epilayer; a mask layer (103) patterned with a plurality of nanosize cavities (102, 102′) disposed on said substrate (101) to form a needle pad; a thin-film (105) of lattice-mismatched semiconductor disposed on said mask layer (103), wherein said thin-film (105) comprises a plurality of in parallel spaced semiconductor needles (104, 204) of said lattice-mismatched semiconductor embedded in said thin-film (105), wherein said plurality of semiconductor needles (104, 204) are substantially vertically disposed in the axial direction toward said substrate (101) in said plurality of nanosize cavities (102, 102′) of said mask layer (103), and where a lattice-mismatched semiconductor epilayer (106) is provided on said thin-film supported thereby.

Provided are a two-dimensional material structure, a semiconductor device including the two-dimensional material structure, and a method of manufacturing the semiconductor device. The two-dimensional material structure may include a first insulator including a first dielectric material; a second insulator on the first insulator and including a second dielectric material; a first two-dimensional material film on an exposed surface of the first insulator; and a second two-dimensional material film provided on an exposed surface of the second insulator. The first and second two-dimensional material films may include a two-dimensional material having a two-dimensional layered structure, and the second two-dimensional material film may include more layers of the two-dimensional material than the first two-dimensional material film.

Gate-all-around integrated circuit structures having underlying dopant-diffusion blocking layers are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires above a fin. The fin includes a dopant diffusion blocking layer on a first semiconductor layer, and a second semiconductor layer on the dopant diffusion blocking layer. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires.

A semiconductor device includes a first channel region disposed over a substrate, a first source region and a first drain region disposed over the substrate and connected to the first channel region such that the first channel region is disposed between the first source region and the first drain region, a gate dielectric layer disposed on and wrapping the first channel region, a gate electrode layer disposed on the gate dielectric layer and wrapping the first channel region, and a second source region and a second drain region disposed over the substrate and below the first source region and the first drain region, respectively. The second source region and the second drain region are in contact with the gate dielectric layer. A lattice constant of the first source region and the first drain region is different from a lattice constant of the second source region and the second drain region.

A negative transconductance device is disclosed. The negative transconductance device includes a first transistor having a P-type semiconductor channel, a second transistor having an N-type semiconductor channel, and a third transistor having an ambipolar semiconductor channel and positioned between the first and second transistors. A first drain electrode of the first transistor is electrically connected to a third source electrode of the third transistor, and a drain electrode of the third transistor is electrically connected to a second source electrode of the second transistor.

Provided are electronic devices and methods of manufacturing the same. An electronic device may include a substrate, a gate electrode on the substrate, a ferroelectric layer between the substrate and the gate electrode, and a carbon layer between the substrate and the ferroelectric layer. The carbon layer may have an sp.sup.2 bonding structure.

A semiconductor structure includes a nanofog oxide adhered to an inert 2D or 3D surface or a weakly reactive metal surface, the nanofog oxide consisting essentially of 0.5-2 nm Al.sub.2O.sub.3 nanoparticles. The nanofog can also consists of sub 1 nm particles. Oxide layers can be formed on the nanofog, for example a bilayer stack of Al.sub.2O.sub.3—HfO.sub.2. Additional examples are from the group consisting of ZrO.sub.2, HfZrO.sub.2, silicon or other doped HfO.sub.2 or ZrO.sub.2, ZrTiO.sub.2, HfTiO.sub.2, La.sub.2O.sub.3, Y.sub.2O.sub.3, Ga.sub.2O.sub.3, GdGaOx, and alloys thereof, including the ferroelectric phases of HfZrO.sub.2, silicon or other doped HfO.sub.2 or ZrO.sub.2. The structure provides the basis for various devices, including MIM capacitors, FET transistors and MOSCAP capacitors.