A microelectronic package can include a substrate having first and second opposed surfaces, and first and second microelectronic elements having front surfaces facing the first surface. The substrate can have a plurality of substrate contacts at the first surface and a plurality of terminals at the second surface. Each microelectronic element can have a plurality of element contacts at the front surface thereof. The element contacts can be joined with corresponding ones of the substrate contacts. The front surface of the second microelectronic element can partially overlie a rear surface of the first microelectronic element and can be attached thereto. The element contacts of the first microelectronic element can be arranged in an area array and are flip-chip bonded with a first set of the substrate contacts. The element contacts of the second microelectronic element can be joined with a second set of the substrate contacts by conductive masses.

A microelectronic package can include a substrate having first and second opposed surfaces, and first and second microelectronic elements having front surfaces facing the first surface. The substrate can have a plurality of substrate contacts at the first surface and a plurality of terminals at the second surface. Each microelectronic element can have a plurality of element contacts at the front surface thereof. The element contacts can be joined with corresponding ones of the substrate contacts. The front surface of the second microelectronic element can partially overlie a rear surface of the first microelectronic element and can be attached thereto. The element contacts of the first microelectronic element can be arranged in an area array and are flip-chip bonded with a first set of the substrate contacts. The element contacts of the second microelectronic element can be joined with a second set of the substrate contacts by conductive masses.

A semiconductor device includes a semiconductor chip, a lead arranged on a side portion of the semiconductor chip, and a wire, whose one end and another end are bonded to the semiconductor chip and the lead respectively, having a ball portion and a stitch portion wedged in side elevational view on the semiconductor chip and the lead respectively. An angle of approach of the wire to the lead is not less than 50, and the length of the stitch portion is not less than 33 m.

A 3D chip packaging structure with a memory device. The memory device includes a memory wafer layer and a connecting layer. The memory wafer layer includes at least one memory partition. The connecting layer is disposed on one side of the memory wafer layer. The connecting layer includes at least one connecting quiet zone and at least one connecting area. The at least one connecting quiet zone and the at least one connecting area are corresponding to the at least one memory partition. The at least one connecting quiet zone is adjacent to the at least one connecting area. The area of the at least one connecting quiet zone is equal to or larger than the at least one connecting area.

A semiconductor device includes a semiconductor chip, a lead arranged on a side portion of the semiconductor chip, and a wire, whose one end and another end are bonded to the semiconductor chip and the lead respectively, having a ball portion and a stitch portion wedged in side elevational view on the semiconductor chip and the lead respectively. An angle of approach of the wire to the lead is not less than 50, and the length of the stitch portion is not less than 33 m.

An electronic package is provided, including a carrier structure, an electronic component disposed on the carrier structure, a heat dissipation structure connected to the electronic component through a thermal interface material, a back side metallization disposed on the electronic component and connected to the thermal interface material, and a liquid metal disposed between the thermal interface material and the back side metallization. A surface viscosity of the liquid metal is used to limit the displacement of the thermal interface material relative to the back side metallization, thereby preventing the heat dissipation structure from being poorly bonding to the electronic component due to misalignment of the thermal interface material, which affects the heat dissipation efficiency of the electronic package.