A semiconductor device includes a semiconductor substrate with a wiring layer formed thereon, an insulating film formed on the semiconductor substrate so as to cover the wiring layer and having a pad opening exposing a portion of the wiring layer as a pad, a front surface protection film formed on the insulating film and being constituted of an insulating material differing from the insulating film and having a second pad opening securing exposure of at least a portion of the pad, a seed layer formed on the pad, and a plating layer formed on the seed layer.

A half bridge circuit includes an input connection configured to supply an electric input, an output connection configured to supply an electric output to a load to be connected to the output connection, a switch and a diode arranged between the input connection and the output connection and a voltage limiting inductance arranged in series between the switch and the diode. The voltage limiting inductance is configured to limit, upon switching the switch, a maximum voltage across the switch to below a breakdown voltage of the switch. A corresponding method of operating the half bridge circuit and package are also described.

A half bridge circuit includes an input connection configured to supply an electric input, an output connection configured to supply an electric output to a load to be connected to the output connection, a switch and a diode arranged between the input connection and the output connection and a voltage limiting inductance arranged in series between the switch and the diode. The voltage limiting inductance is configured to limit, upon switching the switch, a maximum voltage across the switch to below a breakdown voltage of the switch. A corresponding method of operating the half bridge circuit and package are also described.

A pad formed in a semiconductor chip is formed such that a thickness of an aluminum film in a wire bonding portion is smaller than that of an aluminum film in a peripheral portion covered with a protective film. On the other hand, a thickness of a wiring formed in the same step as the pad is larger than that of the pad in the wire bonding portion. The main conductive film of the pad in the wire bonding portion is comprised of only one layer of a first aluminum film, while the main conductive film of the wiring is comprised of at least two layers of aluminum films (the first aluminum film and a second aluminum film) in any region of the wiring.

A semiconductor package for mounting to a printed circuit board (PCB) includes a case comprising a ceramic base, a semiconductor die in the case, a mounting pad under the ceramic base and coupled to the semiconductor die through at least one opening in the ceramic base. The mounting pad includes at least one layer having a coefficient of thermal expansion (CTE) approximately matching a CTE of the ceramic base. The mounting pad includes at least one layer having a low-yield strength of equal to or less than 200 MPa. The mounting pad includes at least one copper layer and at least one molybdenum layer. The semiconductor package also includes a bond pad coupled to another mounting pad under the ceramic base through a conductive slug in the ceramic base.

A semiconductor package for mounting to a printed circuit board (PCB) includes a case comprising a ceramic base, a semiconductor die in the case, a mounting pad under the ceramic base and coupled to the semiconductor die through at least one opening in the ceramic base. The mounting pad includes at least one layer having a coefficient of thermal expansion (CTE) approximately matching a CTE of the ceramic base. The mounting pad includes at least one layer having a low-yield strength of equal to or less than 200 MPa. The mounting pad includes at least one copper layer and at least one molybdenum layer. The semiconductor package also includes a bond pad coupled to another mounting pad under the ceramic base through a conductive slug in the ceramic base.

The present invention relates to a substrate for an optical device, which is configured to connect an optical element substrate and an electrode substrate in a fitting manner, and simultaneously, to form one or more bridge pads which are insulated from the optical element substrate by a horizontal insulating layer, on the optical element substrate. The substrate for an optical device according to a first aspect of the present invention comprises: an optical element substrate which is made of a metal plate and contains a plurality of optical elements therein; a pair of electrode substrates which are made of an insulating material to form a conductive layer on at least a portion of the upper surface thereof, are connected to both side surfaces of the optical element substrate, respectively, and are wire-bonded to the electrodes of the optical elements; and a fitting means which is formed on the side surfaces of the electrode substrate and the optical element substrate to fit the optical element substrate and the electrode substrate. The substrate for an optical device according to a second aspect of the present invention comprises: an optical element substrate which is made of a metal plate and contains a plurality of optical elements therein; a pair of electrode substrates which are made of a metal material to be connected to both side surfaces of the optical element substrate, respectively, and are wire-bonded to the electrodes of the optical elements; a fitting means which is formed on the side surfaces of the electrode substrate and the optical element substrate to fit the optical element substrate and the electrode substrate; and a fitting-type vertical insulating layer which is interposed between the optical element substrate and the electrode substrate so as to be connected to the fitting means.

Techniques for packaging an integrated circuit include attaching a die to a conductive layer before forming dielectric layers on an opposing surface of the conductive layer. The conductive layer may first be formed on a carrier substrate before the die is disposed on the conductive layer. The die may be electrically coupled to the conductive layer via wires or solder bumps. The carrier substrate is removed before the dielectric layers are formed. The dielectric layers may collectively form a coreless package substrate for the integrated circuit package.

A power module substrate 10 is provided with: an insulating substrate 1; and a metal sheet 2 that is joined to the insulating substrate 1 via a brazing material 3, wherein regarding the surface roughness, in the thickness direction, of the lateral surface of the metal sheet 2, the surface roughness of a corner 2a farthest from the center of the metal sheet 2 is larger than the surface roughness of plane parts 2b, which bound the corner, in at least a plan view. Also provided is a power module 100 which is formed by mounting an electronic component 40 on this power module substrate 10.

A solder alloy is providing, the solder alloy including zinc, aluminum, magnesium and gallium, wherein the aluminum constitutes by weight 8% to 20% of the alloy, the magnesium constitutes by weight 0.5% to 20% of the alloy and the gallium constitutes by weight 0.5% to 20% of the alloy, the rest of the alloy including zinc.