An example integrated circuit die includes: lower level conductor layers, lower level insulator layers between the lower level conductor layers, lower level vias extending vertically through the lower level insulator layers, upper level conductor layers overlying the lower level conductor layers, upper level insulator layers between and surrounding the upper level conductor layers, upper level vias; at least two scribe seals arranged to form a vertical barrier extending vertically from the semiconductor substrate to a passivation layer at an upper surface of the integrated circuit die; and at least one opening extending vertically through one of the at least two scribe seals and extending through: the upper level conductor layers, the upper level via layers, the lower level conductor layers, and the lower level via layers.

Some examples described herein provide for a shield in an integrated circuit (IC) structure for memory protection. In an example, an IC structure includes a semiconductor material, an interconnect structure, and a shield. The semiconductor material has a protected region. Devices are disposed in a first side of the semiconductor material in the protected region. The interconnect structure is disposed on the first side of the semiconductor material. The interconnect structure interconnects the devices in the protected region. The shield is disposed on a second side of the semiconductor material opposite from the first side of the semiconductor material. The shield is positioned aligned with the protected region.

Described is a packaging technology to improve performance of an AI processing system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die includes memory and the second die includes computational logic. The first die comprises DRAM having bit-cells. The memory of the first die may store input data and weight factors. The computational logic of the second die is coupled to the memory of the first die. In one example, the second die is an inference die that applies fixed weights for a trained model to an input data to generate an output. In one example, the second die is a training die that enables learning of the weights. Ultra high-bandwidth is changed by placing the first die below the second die. The two dies are wafer-to-wafer bonded or coupled via micro-bumps.

A semiconductor package includes a substrate, an interposer, a primary component layer, a first redistribution layer, multiple solder bumps and a first hybrid bonding structure. The interposer is disposed above the substrate and includes multiple TSV sets. The primary component layer is disposed above the interposer and includes multiple first chips and a first molding material that fills the space between the multiple first chips. The first redistribution layer is disposed between the primary component layer and the interposer and includes at least one portion of an antenna structure. The plurality of solder bumps is disposed between the substrate and the interposer. The first hybrid bonding structure is disposed between the multiple first chips and the multiple TSV sets for electrical connection in between and includes multiple connection components that respectively apply bonding of multiple metal pieces in between.

Three-dimensional integrated circuit component(s) are described including a System-on-a-Chip (SoC) die and a separate static random-access memory (SRAM) subcomponent in a vertically stacked arrangement. Such stacked SoC/SRAM integrated circuit components may form part of a system to render artificial reality images.

A semiconductor package may include vertically-stacked semiconductor chips and first, second, and third connection terminals connecting the semiconductor chips to each other. Each of the semiconductor chips may include a semiconductor substrate, an interconnection layer on the semiconductor substrate, penetration electrodes connected to the interconnection layer through the semiconductor substrate, and first, second, and third groups on the interconnection layer. The interconnection layer may include an insulating layer and first and second metal layers in the insulating layer. The first and second groups may be in contact with the second metal layer, and the third group may be spaced apart from the second metal layer. Each of the first and third groups may include pads connected to a corresponding one of the first and third connection terminals in a many-to-one manner. The second group may include pads connected to the second connection terminal in a one-to-one manner.

A semiconductor device includes a first plurality of dies encapsulated by an encapsulant, an interposer over the first plurality of dies, an interconnect structure over and electrically connected to the interposer, and a plurality of conductive pads on a surface of the interconnect structure opposite the interposer. The interposer includes a plurality of embedded passive components. Each die of the first plurality of dies is electrically connected to the interposer. The interconnect structure includes a solenoid inductor in a metallization layer of the interconnect structure.

A device is provided. The device includes a bridge layer over a first substrate. A first connector electrically connecting the bridge layer to the first substrate. A first die is coupled to the bridge layer and the first substrate, and a second die is coupled to the bridge layer.

An embodiment package includes a first fan-out tier having a first device die, a molding compound extending along sidewalls of the first device die, and a through intervia (TIV) extending through the molding compound. One or more first fan-out redistribution layers (RDLs) are disposed over the first fan-out tier and bonded to the first device die. A second fan-out tier having a second device die is disposed over the one or more first fan-out RDLs. The one or more first fan-out RDLs electrically connects the first and second device dies. The TIV electrically connects the one or more first fan-out RDLs to one or more second fan-out RDLs. The package further includes a plurality of external connectors at least partially disposed in the one or more second fan-out RDLs. The plurality of external connectors are further disposed on conductive features in the one or more second fan-out RDLs.

A method for fabricating a three-dimensional (3D) stacked integrated circuit. Pick-and-place strategies are used to stack the source wafers with device layers fabricated using standard two-dimensional (2D) semiconductor fabrication technologies. The source wafers may be stacked in either a sequential or parallel fashion. The stacking may be in a face-to-face, face-to-back, back-to-face or back-to-back fashion. The source wafers that are stacked in a face-to-back, back-to-face or back-to-back fashion may be connected using Through Silicon Vias (TSVs). Alternatively, source wafers that are stacked in a face-to-face fashion may be connected using Inter Layer Vias (ILVs).