Package structures and methods of forming the same are disclosed. A package structure includes at least one first integrated circuit, at least one second integrated circuit, at least one dummy substrate and an encapsulant. The at least one second integrated circuit is disposed on the at least one dummy substrate in a first direction, and the at least one first integrated circuit and the at least one dummy substrate are separated by a distance in a second direction perpendicular to the first direction. The encapsulant is aside the at least one first integrated circuit, the at least one second integrated circuit and the at least one dummy substrate.

A method includes forming a dielectric layer over a carrier, forming a plurality of bond pads in the dielectric layer, and performing a planarization to level top surfaces of the dielectric layer and the plurality of bond pads with each other. A device die is bonded to the dielectric layer and portions of the plurality of bond pads through hybrid bonding. The device die is encapsulated in an encapsulating material. The carrier is then demounted from the device die and the dielectric layer.

A structure and method of forming are provided. The structure includes a dielectric layer disposed on a substrate. The structure includes a cavity in the dielectric layer, and a plurality of contacts positioned in the cavity and bonded to the substrate. A component is bonded to the plurality of contacts. Underfill is disposed in the cavity between the dielectric layer and the component. A plurality of connectors is on the dielectric layer, the connectors being connected through the dielectric layer to a conductor that is at a same level of metallization as the plurality of contacts.

Disclosed herein is a semiconductor package in which a semiconductor chip and a mounting device are packaged together. The semiconductor package includes a semiconductor chip, a mounting block on which a first mounting device is mounted on a substrate that includes a circuit formed thereon, and an interconnection part configured to electrically connect the semiconductor chip to the mounting block.

A semiconductor package includes a package substrate and semiconductor chips stacked on the package substrate. The package substrate may include at least one first chip enablement finger, at least one second chip enablement finger, and a chip enablement pad selection finger. Each of the semiconductor chips includes a first chip enablement pad connected to the at least one first chip enablement finger, a second chip enablement pad connected to the at least one second chip enablement finger, and a chip enablement pad selection pad connected to the chip enablement pad selection finger. The first chip enablement pads of the semiconductor chips or the second chip enablement pads of the semiconductor chips are optionally activated by a signal applied to the chip enablement pad selection finger.

A method of fabricating an interposer includes: providing a carrier substrate; forming a unit redistribution layer on the carrier substrate, the unit redistribution layer including a conductive via plug and a conductive redistribution line; and removing the carrier substrate from the unit redistribution layer. The formation of the unit redistribution layer includes: forming a first photosensitive pattern layer including a first via hole pattern; forming a second photosensitive pattern layer including a second via hole pattern and a redistribution pattern on the first photosensitive pattern layer; at least partially filling insides of the first via hole pattern, the second via hole pattern, and the redistribution pattern with a conductive material; and performing planarization to make a top surface of the unit redistribution layer flat. According to the method, no undercut occurs under a conductive structure and there are no bubbles between adjacent conductive structures, thus device reliability is enhanced and pattern accuracy is realized.

Disclosed herein is a method of forming a device, comprising mounting a plurality of first interconnects on one or more first integrated circuit dies. One or more second integrated circuit dies are mounted on a first side of an interposer. The interposer is mounted at a second side to the first integrated circuit dies, the plurality of first interconnects disposed outside of the interposer. The interposer is mounted to a first side of a substrate by attaching the first interconnects to the substrate, the substrate in signal communication with one or more of the first integrated circuit dies through the first interconnects.

A semiconductor device according to the present embodiment includes a wiring substrate. A semiconductor chip includes a semiconductor substrate having a first face and a second face on the opposite side to the first face, and an SRAM on the side of the first face, and is stuck to the wiring substrate on the side of the second face. The semiconductor chip includes a first metallic layer provided in the semiconductor substrate between the SRAM and the wiring substrate.

A system-in-package module with memory includes a non-memory chip, a substrate, and a memory chip. The non-memory chip has a first portion and a second portion. The substrate has a window and the substrate is electrically connected to the second portion of the non-memory chip. The memory chip is placed into the window of the substrate to electrically connect the first portion of the non-memory chip, and there is no direct metal connection between the memory chip and the substrate.

A semiconductor package includes a package substrate, a plurality of semiconductor devices stacked on the package substrate, a plurality of underfill fillets disposed between the plurality of semiconductor devices and between the package substrate and the plurality of semiconductor devices, and a molding resin at least partially surrounding the plurality of semiconductor devices and the plurality of underfill fillets. The plurality of underfill fillets include a plurality of protrusions that protrude from spaces between each of the plurality of semiconductor devices or between the package substrate and each of the plurality of semiconductor devices. At least two neighboring underfill fillet protrusions of the plurality of protrusions form one continuous structure without an interface therebetween.