A package base substrate includes a base layer; a plurality of lower surface connection pads disposed on a lower surface of the base layer; a plurality of lower surface wiring patterns disposed on a lower surface of the base layer and respectively connected to a set of lower surface connection pads of the plurality of lower surface connection pads; and a lower surface solder resist layer covering a portion of each of the plurality of lower surface connection pads and the plurality of lower surface wiring patterns on a lower surface of the base layer, wherein each of at least some of the lower surface connection pads of the set of lower surface connection pads has a teardrop shape in a plan view, and includes a ball land portion having a planar circular shape, including a terminal contact portion exposed without being covered by the lower surface solder resist layer, and an edge portion surrounding the terminal contact portion and covered by the lower surface solder resist layer; and a connection reinforcement portion between the ball land portion and the lower surface wiring pattern, including an extension line portion having a width that is the same as a line width of the lower surface wiring pattern and extending from the ball land portion to the lower surface wiring pattern, and a corner reinforcement portion filling a corner between the ball land portion and the extension line portion, and wherein an extension length of the extension line portion has a value greater than a radius of the terminal contact portion.

A method of manufacturing a vertical memory device includes forming a first sacrificial layer on a substrate, the first sacrificial layer including a first insulating material, forming a mold including an insulation layer and a second sacrificial layer alternately and repeatedly stacked on the first sacrificial layer, the insulation layer and the second sacrificial layer including second and third insulating materials, respectively, different from the first insulating material, forming a channel through the mold and the first sacrificial layer, forming an opening through the mold and the first sacrificial layer to expose an upper surface of the substrate, removing the first sacrificial layer through the opening to form a first gap, forming a channel connecting pattern to fill the first gap, and replacing the second sacrificial layer with a gate electrode.

A bonded assembly includes a first semiconductor die containing a first substrate, first semiconductor devices, and first bonding pads laterally surrounded by a first pad-level dielectric layer. The first pad-level dielectric layer includes at least one first encapsulated airgap located between neighboring pairs of first bonding pads and encapsulated by a first dielectric fill material of the first pad-level dielectric layer. The bonded assembly includes a second semiconductor die containing a second substrate, second semiconductor devices, and second bonding pads laterally surrounded by a second pad-level dielectric layer. Each of the second bonding pads is bonded to a respective one of the first bonding pads.

A semiconductor assembly includes a first die and a second die. The semiconductor assembly also includes a film on die (FOD) layer configured to attach the first die to the second die. The FOD layer is disposed on a first surface of the first die. The FOD layer includes a first portion comprising a first die attach film (DAF) disposed on an inner region of the first surface. The FOD layer also includes a second portion that includes a second DAF disposed on a peripheral region of the first surface surrounding the inner region. The second DAF includes a different material than the first DAF.

An embedded module according to the present invention includes a base substrate having a multi-layer wiring, at least two semiconductor chip elements having different element thicknesses, each of the semiconductor chip element having a first surface fixed to the base substrate and having a connection part on a second surface, an insulating photosensitive resin layer enclosing the semiconductor chip elements on the base substrate and being formed by a first wiring photo via, a second wiring photo via, and a wiring, the first wiring photo via electrically connected to the connection part of the semiconductor chip elements, the second wiring photo via arranged at the outer periphery of each of the semiconductor chip elements and electrically connected to a connection part of the base substrate, the wiring arranged so as to be orthogonal to and electrically connected to the first wiring photo via and the second wiring photo via.

A packaging technology to improve performance of an AI processing system resulting in an ultra-high bandwidth system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die can be a first logic die (e.g., a compute chip, CPU, GPU, etc.) while the second die can be a compute chiplet comprising ferroelectric or paraelectric logic. Both dies can include ferroelectric or paraelectric logic. The ferroelectric/paraelectric logic may include AND gates, OR gates, complex gates, majority, minority, and/or threshold gates, sequential logic, etc. The IC package can be in a 3D or 2.5D configuration that implements logic-on-logic stacking configuration. The 3D or 2.5D packaging configurations have chips or chiplets designed to have time distributed or spatially distributed processing. The logic of chips or chiplets is segregated so that one chip in a 3D or 2.5D stacking arrangement is hot at a time.

A wafer-level ASIC 3D integrated substrate, a packaging device and a preparation method are disclosed. The substrate includes a first wiring layer conductive pillars, a molding layer, a second wiring layer, a bridge IC structure and solder balls. The first wiring layer includes a first dielectric layer and a first metal wire layer. The second wiring layer includes a second dielectric layer and a second metal wire layer. The conductive pillars are disposed between the first wiring layer and the second wiring layer, two ends of each of the conductive pillars are electrically connected to the first metal wire layer and the second metal wire layer, respectively. The bridge IC structure is electrically connected to at least one conductive pillar. The molding layer molds the conductive pillars and the bridge IC structure. The solder balls are disposed on a side of the second wiring layer and electrically connected to the second metal wire layer.

According to one embodiment, a semiconductor device includes a substrate, first stacked components, second stacked components, and a coating resin. The first stacked components include first chips and are stacked on a surface of the substrate. The second stacked components include second chips and are stacked on the surface. The coating resin covers the surface, the first stacked components, and the second stacked components. A first top surface of a second farthest one of the first chips away from the surface differs in position in a first direction from a second top surface of second farthest one of the second chips away from the surface.

A memory device is disclosed. The disclosed memory device may include a first wafer, and a second wafer stacked on and bonded to the first wafer. The first wafer may include a cell structure including a memory cell array; and a first logic structure disposed under the cell structure, and including a column control circuit. The second wafer may include a second logic structure including a row control circuit.

A method includes forming a first through-via from a first conductive pad of a first device die, and forming a second through-via from a second conductive pad of a second device die. The first and second conductive pads are at top surfaces of the first and the second device dies, respectively. The first and the second conductive pads may be used as seed layers. The second device die is adhered to the top surface of the first device die. The method further includes encapsulating the first and the second device dies and the first and the second through-vias in an encapsulating material, with the first and the second device dies and the first and the second through-vias encapsulated in a same encapsulating process. The encapsulating material is planarized to reveal the first and the second through-vias. Redistribution lines are formed to electrically couple to the first and the second through-vias.