Aspects of the disclosure provide a semiconductor device and a method to fabricate the semiconductor device. The semiconductor device includes a first die comprising a first contact structure formed on a face side of the first die. The semiconductor device includes a first semiconductor structure and a first pad structure that are disposed on a back side of the first die. The first semiconductor structure is conductively connected with the first contact structure from the back side of the first die and the first pad structure is conductively coupled with the first semiconductor structure. An end of the first contact structure protrudes into the first semiconductor structure without connecting to the first pad structure. The first die and a second die can be bonded face-to-face.

A semiconductor memory device includes a semiconductor substrate including a first circuit group and a second circuit group spaced apart from each other. The memory device also includes a memory cell array overlapping with the semiconductor substrate. The memory device further includes a vertical conductive line crossing the memory cell array, the vertical conductive line being connected to the first circuit group and the second circuit group.

A semiconductor memory device including a substrate having a first region and a second region; a plurality of first transistors provided in the first region; a plurality of second transistors provided in the second region, the plurality of second transistors being electrically coupled to the plurality of first transistors, respectively, and a breakdown-voltage of the second transistor being lower than a breakdown-voltage of the first transistor. A plurality of joint metals are provided above the first region, the plurality of joint metals being electrically coupled to the plurality of first transistors, respectively. A plurality of bit lines are provided in an upper layer of the plurality of joint metals, the plurality of bit lines being coupled to the plurality of joint metals, respectively; and a plurality of memory cells are provided in an upper layer of the plurality of bit lines, the plurality of memory cells being coupled to the plurality of bit lines, respectively.

A three-dimensional fan-out integrated package structure, a packaging method thereof, and a wireless headset are disclosed. The three-dimensional fan-out integrated package structure includes a first rewiring layer, a second rewiring layer, a metal connection pillar, a first semiconductor chip, a second semiconductor chip, a first filler layer, a first encapsulating layer, a functional chip, a second filler layer, a second encapsulating layer, and metal bumps. By stacking two semiconductor chips, the structure can effectively reduce the packaging area and realize device packaging with high density and high integration, while enabling the minimum line width/line spacing to be reduced to 1.5 μm/1.5 μm. In addition, the three-dimensional fan-out integrated package structure can simultaneously integrate various functional chips and components such as GPU/PMU/DDR/mm-wave antenna/capacitor/inductor/transistor/flash memory/filter to realize system-level packaging, which not only can reduce cost but also improve the effectiveness of the package structure by using physical isolation to reduce device interference.

Semiconductor devices with controllers under stacks of semiconductor packages and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a package substrate, a controller attached to the package substrate, and at least two semiconductor packages disposed over the controller. Each semiconductor package includes a plurality of semiconductor dies. The semiconductor device further includes an encapsulant material encapsulating the controller and the at least two semiconductor packages.

A method includes forming a first through-via from a first conductive pad of a first device die, and forming a second through-via from a second conductive pad of a second device die. The first and second conductive pads are at top surfaces of the first and the second device dies, respectively. The first and the second conductive pads may be used as seed layers. The second device die is adhered to the top surface of the first device die. The method further includes encapsulating the first and the second device dies and the first and the second through-vias in an encapsulating material, with the first and the second device dies and the first and the second through-vias encapsulated in a same encapsulating process. The encapsulating material is planarized to reveal the first and the second through-vias. Redistribution lines are formed to electrically couple to the first and the second through-vias.

A semiconductor package includes; a redistribution wiring layer, a controller chip centrally disposed on the redistribution wiring layer, a first sealant disposed on the redistribution wiring layer, wherein the controller chip is buried in the first sealant, through vias connected to the redistribution wiring layer through the first sealant, and a sub-package disposed on an upper surface of the first sealant. The sub-package may include a first stack structure disposed to one side of the controller chip on the upper surface of the first sealant and including vertically stacked chips, a second stack structure disposed to another side of the controller chip on the upper surface of the first sealant adjacent to the first stack structure in a first horizontal direction and including vertically stacked chips, and a second sealant sealing the first stack structure and the second stack structure.

A semiconductor package includes a substrate having a passive element region, a peripheral region adjacent to the passive element region, and a remaining region, a first passive element on an upper surface of the passive element region, a first semiconductor chip on an upper surface of the remaining region, and a sealing portion covering the substrate, the first passive element, and the first semiconductor chip, wherein the peripheral region includes a first sub-region on a first side of the first passive element, a second sub-region on a second side opposite the first side, a third sub-region on a third side of the first passive element, and a fourth sub-region on a fourth side opposite the third side, and wherein a roughness of an upper surface of at least one of the first to fourth sub-regions is greater than a roughness of the upper surface of the remaining region.

A semiconductor package includes a package substrate that includes a substrate base and a lower solder resist layer that covers a lower surface of the substrate base, where the lower solder resist layer includes a ponding recess that extends from a lower surface toward an upper surface of the lower solder resist layer, a semiconductor chip attached to an upper surface of the package substrate, an auxiliary chip attached to a lower surface of the package substrate adjacent to the ponding recess through a plurality of chip terminals, where the auxiliary chip includes a first side and a second side opposite to each other in a plane, and an underfill layer that fills a space between the package substrate and the auxiliary chip, surrounds the plurality of chip terminals, and fills the ponding recess.

A bonded assembly includes a first semiconductor die that includes first metallic bonding structures embedded within a first bonding-level dielectric layer, and a second semiconductor die that includes second metallic bonding structures embedded within a second bonding-level dielectric layer and bonded to the first metallic bonding structures by metal-to-metal bonding. One of the first metallic bonding structures a pad portion, and a via portion located between the pad portion and the first semiconductor device, the via portion having second tapered sidewalls.