A semiconductor module includes a first semiconductor die, which comprises (i) a power support structure and (ii) a first cache region; and a second semiconductor die, which is mounted on top of the first semiconductor die and comprises (i) a logic core, which overlies and is electrically connected to the power support structure, and (ii) a second cache region, which overlies and is electrically connected to the first cache region.

In certain aspects, a memory device includes a vertical transistor, a storage unit, a bit line, and a body line. The vertical transistor includes a semiconductor body extending in a first direction. The semiconductor body includes a doped source, a doped drain, and a channel portion. The storage unit is coupled to a first terminal. The first terminal is one of the source and the drain. The bit line extends in a second direction perpendicular to the first direction and coupled to a second terminal. The second terminal is another one of the source and the drain. The body line is coupled to the channel portion of the semiconductor body.

A semiconductor structure includes an alternating stack of insulating layers and composite layers. Each of the composite layers includes a plurality of electrically conductive word line strips laterally extending along a first horizontal direction and a plurality of dielectric isolation strips laterally extending along the first horizontal direction and interlaced with the plurality of electrically conductive word line strips. Rows of memory openings are arranged along the first horizontal direction. Each row of memory openings vertically extends through each insulating layer within the alternating stack and one electrically conductive strip for each of the composite layers. Rows of memory opening fill structures are located within the rows of memory openings. Each of the memory opening fill structures includes a respective vertical stack of memory elements and a respective vertical semiconductor channel.

A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers located on a semiconductor layer, a memory opening vertically extending through the alternating stack and the semiconductor layer, a memory opening fill structure located in the memory opening and containing a memory film and a vertical semiconductor channel, and a backside semiconductor source structure including a doped semiconductor material. The backside semiconductor source structure may be polycrystalline or single crystalline.

A memory device includes a vertical transistor including a semiconductor body extending in a first direction. The semiconductor body includes a doped source, a doped drain, and a channel portion. The memory device further includes a storage unit coupled to one of the source and the drain, a word line extending in a second direction perpendicular to the first direction, and a body line coupled to the channel portion of the semiconductor body. The word line is between the storage unit and the body line in the first direction.

A semiconductor device and method for forming thereof is provided. The semiconductor device includes vertical transistors, storage units, and a bonding layer. Each vertical transistor includes a semiconductor layer and a gate structure. The semiconductor layer has a leakage value lower than a pico-ampere and extends along a vertical direction. The gate structure is coupled with one side of the semiconductor layer. Each storage unit is coupled with the semiconductor layer of the vertical transistor. The bonding layer is configured to couple the vertical transistors with a peripheral circuit. The vertical transistors are disposed between the bonding layer and the storage units.