A direct current (DC) to DC (DC-DC) converter includes a comparator setting a pulse width of a signal pulse, the pulse width corresponding to a voltage level of an output voltage of the DC-DC converter; a digital delay line (DDL) operatively coupled to the comparator, the DDL adjusting the pulse width of the signal pulse by linearly introducing delays to the signal pulse; a multiplexer operatively coupled to the DDL, the multiplexer selectively outputting a delayed version of the signal pulse; a phase detector operatively coupled to a system clock and the multiplexer, the phase detector generating a phase error between an output of the multiplexer and the system clock; and a logic control circuit operatively coupled to the multiplexer and the DDL, the logic control circuit adjusting the delay introduced to the signal pulse in accordance with the phase error.

To provide a semiconductor device with a digital-controlled DC-DC converter capable of stable feedback operation while minimizing area, the semiconductor device includes a DC-DC converter whose characteristic is determined by the control parameter, a flash memory and a processor that controls the flash memory, both of which operate at a power supply based on the output of the DC-DC converter. The control parameter is stored in the flash memory, and the control parameter is read out from the flash memory and set in the DC-DC converter by the processor while the DC-DC converter is operating.

To provide a semiconductor device with a digital-controlled DC-DC converter capable of stable feedback operation while minimizing area, the semiconductor device includes a DC-DC converter whose characteristic is determined by the control parameter, a flash memory and a processor that controls the flash memory, both of which operate at a power supply based on the output of the DC-DC converter. The control parameter is stored in the flash memory, and the control parameter is read out from the flash memory and set in the DC-DC converter by the processor while the DC-DC converter is operating.

An electronic circuit includes a first peak-hold circuit to output a peak surge voltage free of a ringing component included in a voltage at a voltage input node, a second peak-hold circuit to output a peak surge voltage on which the ringing component included in the voltage at the voltage input node is superimposed, and a subtractor to subtract an output voltage of the first peak-hold circuit from an output voltage of the second peak-hold circuit to output a voltage of the ringing component.

The present document relates to a power converter configured to generate an output voltage at an output of the power converter. The power converter may comprise a power stage, a modulator circuit, ramp generator circuit, a first feedback circuit, and a second feedback circuit. The power stage may be coupled to the output of the power converter. The modulator circuit may comprise a first input and a second input, and an output of the modulator circuit may be coupled to the power stage. The ramp generator circuit may be configured to generate a ramp signal, and an output of the ramp generator circuit may be coupled to the first input of the modulator circuit. The first feedback loop may be coupled between the output of the power converter and the second input of the modulator circuit.

The present document relates to a power converter configured to generate an output voltage at an output of the power converter. The power converter may comprise a power stage, a modulator circuit, ramp generator circuit, a first feedback circuit, and a second feedback circuit. The power stage may be coupled to the output of the power converter. The modulator circuit may comprise a first input and a second input, and an output of the modulator circuit may be coupled to the power stage. The ramp generator circuit may be configured to generate a ramp signal, and an output of the ramp generator circuit may be coupled to the first input of the modulator circuit. The first feedback loop may be coupled between the output of the power converter and the second input of the modulator circuit.

A main circuit includes a switching element, and converts electric power input to the main circuit and supplies a result of the conversion to a load. The controller switches a control scheme of the main circuit from a first control scheme to a second control scheme at a first time point when the output value starts to vary and switches the control scheme of the main circuit from the second control scheme to the first control scheme at a second time point when a determination is made that switching of a variation direction of the output value will occur on the basis of a detection value of the detector.

A main circuit includes a switching element, and converts electric power input to the main circuit and supplies a result of the conversion to a load. The controller switches a control scheme of the main circuit from a first control scheme to a second control scheme at a first time point when the output value starts to vary and switches the control scheme of the main circuit from the second control scheme to the first control scheme at a second time point when a determination is made that switching of a variation direction of the output value will occur on the basis of a detection value of the detector.

Subject matter disclosed herein may relate to semiconductor devices, and may more particularly relate to power semiconductor packages, for example.

The present invention relates to a DC-DC power converter which comprises a switched converter core operated in accordance with a primary control signal to supply a primary DC output current (Io) of the converter; said primary control signal exhibiting a minimum resolution, e.g. a minimum time step, leading to a corresponding minimum current step of the primary DC output current. The DC-DC power converter additionally comprises a controllable resistive path, or a controllable current source, connected between a pair of terminals selected from a group of: (the positive output terminal, the negative output terminal, the positive input terminal, the negative input terminal) and configured to add or subtract a secondary DC output current (Icon) to the primary DC output current (Io) in accordance with a secondary control signal to adjust the load current.