A resonant power converter controller comprising a control circuit configured to turn on a synchronous rectifier (SR) in response to a count of a number of times a drain voltage of the SR crosses below a turn on threshold based on a stored count and turns off the SR when the drain voltage crosses above a turn off threshold. The control circuit comprises a first comparator configured to generate a first detection signal in response to the drain voltage being less than the turn on threshold. A first turn on detection circuit generates a first turn on signal when the count reaches the stored count. A first turn off signal is generated in response to the drain voltage being greater than the turn off threshold. A drive circuit turns on and off the SR in response to the first turn on signal and the first turn off signal.

A synchronous rectifier control apparatus includes a continuous conduction mode detection circuit configured to receive a voltage across a synchronous rectifier switch and determine whether the synchronous rectifier switch operates in a continuous conduction mode based on a rising slope of the voltage across the synchronous rectifier switch, a turn-off timer control circuit configured to measure a conduction time of the synchronous rectifier switch and turn off the synchronous rectifier switch after the conduction time of the synchronous rectifier switch in a current cycle is substantially equal to the conduction time measured in an immediately previous cycle, and a drive voltage control circuit configured to reduce a gate drive voltage of the synchronous rectifier switch after the conduction time of the synchronous rectifier switch in the current cycle is substantially equal to the conduction time measured in the immediately previous cycle multiplied by a predetermined percentage.

A secondary side controller of a flyback AC-DC converter includes an integrated circuit, which includes: an analog-to-digital converter (ADC) coupled to a voltage bus (VBUS), the ADC to output a digital value corresponding to a voltage level of the VBUS; first logic configured to generate a reference voltage based on the digital value; second logic configured to generate a VBUS gain value based on output power of a flyback transformer of the flyback AC-DC converter; an integrator to accumulate current corresponding to a sensed voltage at a drain of a synchronous rectifier (SR) of a secondary side of the flyback transformer, the accumulated current to be modified according to the VBUS gain value, wherein the integrator outputs an updated sensed voltage; and a comparator to output a detection signal, indicative of a negative sense voltage, in response to the updated sensed voltage matching the reference voltage.

A power converter controller includes an analog to digital converter (ADC) to generate a digital representation of a feedback signal of a power converter, the feedback signal being received from a compensator of the power converter and being based on an output voltage of the power converter. A nonlinear gain block of the power converter controller receives the digital representation of the feedback signal and generates a transformed digital representation of the feedback signal using a nonlinear function. A switch control block of the power converter controller controls an on-time of a primary-side switch of the power converter based on the transformed digital representation of the feedback signal.

An example a circuit for controlling a power converter comprises a first power domain circuit including a first control circuit and a first driver circuit, wherein the first control circuit controls the first driver circuit to drive a first semiconductor device, wherein a second power domain circuit includes a second control circuit and a second driver circuit. The first control circuit is configured to receive a control signal for controlling the second driver circuit to drive a second semiconductor device; and identify, based on the control signal, a future electrical characteristic of a second power domain output of the power converter. Additionally, the first control circuit is configured to determine, based on the future electrical characteristic of the second power domain output of the power converter, whether to adjust one or more control parameters for controlling the first driver circuit to drive the first semiconductor device.

Systems and methods for voltage compensation based on load conditions in power converters. For example, a system controller for regulating a power converter includes a first controller terminal; a second controller terminal; and a compensation current generator. The compensation current generator is configured to receive an input signal through the first controller terminal. The input signal indicates a first current flowing through a primary winding of a power converter. The compensation current generator is configured to receive a demagnetization signal related to a demagnetization period of the power converter and associated with an auxiliary winding of the power converter. The compensation current generator is configured to generate a compensation current based at least in part on the input signal and the demagnetization signal. The compensation current generator is connected to a resistor. The resistor is configured to generate a compensation voltage based at least in part on the compensation current.

A fast load current sensing apparatus and scheme provides instantaneous detection of peak current excursions using low silicon area and power efficient techniques. The response time for detecting signal excursions and measuring a signal (e.g., load current) is independent of resolution or precision and can be applied to high resolution telemetry. The apparatus sends out maximum current limit (FHC_limit) code at any instant the load current is detected to be more than a digital-to-analog converter (DAC) code. If the load current is less than the FHC_limit the scheme restores to a next DAC code as per a counter's next value. In case load current is more than FHC_limit, the scheme updates the DAC code to FHC_limit code and starts the counter from the FHC_limit.

A current detection circuit capable of compensating for detection accuracy of a switching current through switching of a connection state of a resistor even when the switching current has a component in a direction opposite to a predetermined direction is provided. A current detection circuit for detecting a value of a component in a predetermined direction of a switching current using a current transformer, wherein, when the switching current flowing in a primary side of the current transformer has a component in a direction opposite to the predetermined direction, a connection state of reset elements on a secondary side of the current transformer is switched such that an impedance of a magnetic reset on the secondary side of the current transformer is decreased.

A driving circuit including a reference voltage generator to generate a reference voltage based on an operating frequency of a complementary circuit; a comparator including a first input configured to receive a drain-to-source voltage of a field effect transistor; and a second input to receive the reference voltage; and a signal generator to deliver a driving signal to a gate terminal of the field effect transistor to drive the field effect transistor to an ON state after the drain-to-source voltage of the first low side field effect transistor becomes less than the reference voltage and to an OFF state after the drain-to-source voltage of the field effect transistor becomes greater than the reference voltage.

A method for communicating with a power converter comprises initiating a communication sequence by sensing a first distortion of a sensed waveform during a discharge period of a first power transfer cycle of the power converter. The sensed waveform is proportional to a secondary current of the power converter. At a primary side of the power converter, a data bit is received from a secondary side of the power converter, by sensing a second distortion to represent one state of the data bit and sending an absence of the second distortion to represent another state of the data bit. The secondary distortion is applied to the secondary current during the discharge period of a subsequent power transfer cycle.