An alternating current (AC) to direct current (DC) power converter may have a connector with a pair of power supply contacts and a pair of data contacts. An electronic device may be connected to the connector of the power converter. The power converter may supply DC power to the electronic device using the power supply contacts. The power converter may include control circuitry that has a resistor coupled across the data contacts. When the electronic device and the power converter are connected to each other, each may advertise to the other that capabilities are present that exceed industry standards. At the same time, standard-compliant discovery operations may be performed to probe the value of the resistance of the resistor that is coupled across the data contacts. When extended capabilities are discovered, extended functions may be performed including accelerated charging functions and data communications functions.

An inverter. The inverter includes a first and second transistors, which are a high-side transistor and a low-side transistor of the inverter, and control electronics configured to trigger a first switching operation, in which the first transistor is switched on, wherein the second transistor is in a switched-off state, wherein a parasitic capacitance of the first transistor is discharged during the first switching operation, to trigger a second switching operation, in which the first transistor is switched off or switched on again, wherein the second transistor simultaneously remains in the switched-off state, wherein the parasitic capacitance of the first transistor is already discharged in the second switching operation, to record a time difference which describes a difference between a duration of the first switching operation and a duration of the second switching operation, and to determine a characteristic operating parameter of the first transistor based on the time difference.

An apparatus may include a first device having a first metal structure, a first metal element, and a first transistor. The first metal structure may include first and second surfaces, that are flat and opposite facing. The first metal element may include first and second surfaces that are flat and opposite facing. The first transistor may include first and second terminals between which 1 amp or more of electrical current is transmitted when the first transistor is activated, wherein the first and second terminals may include first and second surfaces, respectively, that are substantially flat and opposite facing. The second surface of the first metal structure can be electrically and thermally connected to a bus bar. The first and second surfaces of the first and second terminals, respectively, may be sintered to the first and second surfaces, respectively, of the first metal structure and the first metal element, respectively.

A wireless charging control circuit includes at least one control sub-circuit. Each control sub-circuit is configured to, prior to turn-on of a target switching transistor based on a received PWM signal, send a pulse width adjustment instruction to a signal processor corresponding to the target switching transistor based on a voltage difference between a first terminal and a second terminal of the target switching transistor, to instruct the signal processor to adjust a pulse width of a next PWM signal input to the target switching transistor. In this way, the wireless charging control circuit is capable of adaptively regulating the pulse width of the PWM signal, which avoids excessively large or small dead times, such that electromagnetic interference is prevented and conversion efficiency of a charging circuit is improved.

An apparatus may include a first device having a first metal structure, a first metal element, and a first transistor. The first metal structure may include first and second surfaces, that are flat and opposite facing. The first metal element may include first and second surfaces that are flat and opposite facing. The first transistor may include first and second terminals between which 1 amp or more of electrical current is transmitted when the first transistor is activated, wherein the first and second terminals may include first and second surfaces, respectively, that are substantially flat and opposite facing. The second surface of the first metal structure can be electrically and thermally connected to a bus bar. The first and second surfaces of the first and second terminals, respectively, may be sintered to the first and second surfaces, respectively, of the first metal structure and the first metal element, respectively.

A self-biasing inverter and a control method thereof related to the self-biasing inverter are provided. The self-biasing inverter includes a power terminal configured to receive a working power, an input terminal configured to receive an input signal, an output terminal configured to output an output signal related to the input signal, a first transistor electrically connected between the power terminal and the output terminal, a second transistor electrically connected between the output terminal and a ground terminal, a capacitor electrically connected between the input terminal and a node, a switch unit connected to the capacitor in parallel, and an impedance assembly electrically connected between the node and the output terminal. A control terminal of the first transistor is electrically connected to node. A control terminal of the second transistor is electrically connected to the node.

A self-biasing inverter and a control method thereof related to the self-biasing inverter are provided. The self-biasing inverter includes a power terminal configured to receive a working power, an input terminal configured to receive an input signal, an output terminal configured to output an output signal related to the input signal, a first transistor electrically connected between the power terminal and the output terminal, a second transistor electrically connected between the output terminal and a ground terminal, a capacitor electrically connected between the input terminal and a node, a switch unit connected to the capacitor in parallel, and an impedance assembly electrically connected between the node and the output terminal. A control terminal of the first transistor is electrically connected to node. A control terminal of the second transistor is electrically connected to the node.