A low voltage differential signaling receiver includes a resistor load pair, an input stage, a current mode logic stage and a comparator circuit. The input stage includes a P-type transistor pair and a N-type transistor pair. The P-type transistor pair and the N-type transistor pair are configured to generate first differential output voltages on the resistor load pair according to differential input signals. The current mode logic stage is configured to enhance a gain of the first differential output voltages into second differential output voltages. The latch circuit is configured to generate third differential output voltages according to the second differential output voltages and latch the third differential output voltages. The comparator circuit is configured to compare the third differential output voltages and generate a single-ended output signal.

A method and system for amplifying small optical currents in an optical receiver front end system may employ multiple transimpendance amplifiers (TIAs) and feedback control loops. For example, the front end system may include a main feedback control loop (having a main TIA) and a replica feedback control loop (having a replica TIA) that, collectively, generate an optimum input common mode level for a differential amplifier operating at high data rates (e.g., speeds up to tens of gigabits per second). The replica TIA may track the noise from the power supply of the optical receiver in the substantially same manner as the main TIA. Therefore, the differential signals produced by the main control loop may not be degraded at the input to the high-speed differential amplifier. The outputs of the high-speed differential amplifier may be symmetric about the common mode level and may be suitable inputs for voltage sampling.

A method and system for amplifying small optical currents in an optical receiver front end system may employ multiple transimpendance amplifiers (TIAs) and feedback control loops. For example, the front end system may include a main feedback control loop (having a main TIA) and a replica feedback control loop (having a replica TIA) that, collectively, generate an optimum input common mode level for a differential amplifier operating at high data rates (e.g., speeds up to tens of gigabits per second). The replica TIA may track the noise from the power supply of the optical receiver in the substantially same manner as the main TIA. Therefore, the differential signals produced by the main control loop may not be degraded at the input to the high-speed differential amplifier. The outputs of the high-speed differential amplifier may be symmetric about the common mode level and may be suitable inputs for voltage sampling.

A class-D amplifier includes a loop filter, a pulse-width modulation (PWM) circuit, an output circuit, and a common-mode control circuit. The loop filter receives an input signal of the class-D amplifier to generate a filtered signal. The PWM circuit converts a non-PWM signal into a PWM signal, wherein the non-PWM signal is derived from at least the filtered signal. The output circuit generates an output signal of the class-D amplifier according to the PWM signal. The common-mode control circuit monitors a common-mode level of the output signal to generate a common-mode control signal for PWM common-mode control.

Examples of circuitry and systems and methods provide a multi-way configurable amplifier to support various applications. The multi-way configurable amplifier may include a reconfigurable filter that comprises first and second inputs adapted to receive an input signal; a fully differential amplifier (FDA); and first and second reconfigurable resistance-capacitance (RC) networks. The FDA has an inverting input, a non-inverting input, an inverting output, and a non-inverting output. The inverting input is coupled to the first input, and the non-inverting input is coupled to the second input. The first reconfigurable RC network is coupled to the non-inverting output, and the second reconfigurable RC network is selectively couplable to the inverting output. The reconfigurable filter is configurable to enable operation in any of multiple modes including a single-ended mode of operation and a differential mode of operation.

The present disclosure relates to circuitry comprising audio amplifier circuitry for receiving an audio signal to be amplified; and first and second output nodes for outputting first and second differential output signals. The circuitry further comprises common mode buffer circuitry configured to receive a common mode voltage and to selectively output the common mode voltage to the first and second output nodes.

A sample-and-hold amplifier can include: an operational amplifier; a sampling capacitor having a first terminal coupled to an inverting input terminal of the operational amplifier, and a second terminal coupled to a reference ground; and a switching circuit configured to switch feedback paths of the sample-and-hold amplifier in a first stage and a second stage, such that an offset voltage of the operational amplifier is at least partially eliminated.

A low voltage differential signaling receiver includes a resistor load pair, an input stage, a current mode logic stage and a comparator circuit. The input stage includes a P-type transistor pair and a N-type transistor pair. The P-type transistor pair and the N-type transistor pair are configured to generate first differential output voltages on the resistor load pair according to differential input signals. The current mode logic stage is configured to enhance a gain of the first differential output voltages into second differential output voltages. The latch circuit is configured to generate third differential output voltages according to the second differential output voltages and latch the third differential output voltages. The comparator circuit is configured to compare the third differential output voltages and generate a single-ended output signal.

A transconductance-transimpedance (TAS-TIA) amplifier includes a TAS amplifier, a TIA amplifier, and a first common-mode feedback (CMFB) circuit. The TIA amplifier includes a first transistor and a second transistor. The first transistor is coupled between a first TIA output node and a reference voltage. The second transistor is coupled between a second TIA output node and the reference voltage. The first CMFB circuit has a first operational amplifier, a first capacitor, and a first resistor. The first operational amplifier has a first input node for receiving a TIA output common-mode voltage, a second input node, and a first output node coupled to control terminals of the first and second transistors. The first capacitor is coupled between the first output node and the second input node of the first operational amplifier. The first resistor is coupled between the second input node of the first operational amplifier and a reference common-mode voltage.

A low voltage differential signaling receiver includes a resistor load pair, an input stage, a current mode logic stage and a comparator circuit. The input stage includes a P-type transistor pair and a N-type transistor pair. The P-type transistor pair and the N-type transistor pair are configured to generate first differential output voltages on the resistor load pair according to differential input signals. The current mode logic stage is configured to enhance a gain of the first differential output voltages into second differential output voltages. The latch circuit is configured to generate third differential output voltages according to the second differential output voltages and latch the third differential output voltages. The comparator circuit is configured to compare the third differential output voltages and generate a single-ended output signal.