A feedback stage for an integrator circuit is provided. The integrator receives a first input current and a second input current that include respective measurement current components and an offset current component. The integrator integrates the first input current and the second input current and generates a first output voltage and a second output voltage. The feedback stage including a transconductance amplifier detects a difference between the first output voltage and the second output voltage and sinks or sources a first output current and a second output current based on the difference between the first output voltage and the second output voltage. The first output current is additively combined with the first input current and the second output current is additively combined with the second input current to mitigate the offset current component at an input of the integrator.

To provide a semiconductor device that makes it possible to reduce a cell circuit area and an increase in resolution. There is provided a semiconductor device including: a first region in which readout cells are arranged in an array form, the readout cells having one of input transistors included in a differential amplifier: and a second region in which reference cells are arranged in an array form, the reference cells having another input transistor included in the differential amplifier, the first region and the second region being separated from each other.

An amplification interface includes a drain of a first FET connected to a first node, a drain of a second FET connected to a second node, and sources of the first and second FETs connected to a third node. First and second bias-current generators are connected to the first and second nodes. A third FET is connected between the third node and a reference voltage. A regulation circuit drives the gate of the third FET to regulate the common mode of the voltage at the first node and the voltage at the second node to a desired value. A current generator applies a correction current to the first and/or second node. A differential current integrator has a first and second inputs connected to the second and first nodes. The integrator supplies a voltage representing the integral of the difference between the currents received at the second and first inputs.

The present invention corresponds to a method and a circuit for compensating the offset voltage of electronic circuits, where the circuit implementing the method comprises: a dynamic comparator (1); a phase detector (6) connected to the dynamic comparator (1), the phase detector (6); a finite-state machine (9) connected to the phase detector (4), a first digital-analog converter (12) connected to an output of the finite-state machine (9); a second digital-analog converter (13) connected to another output (11) of the finite-state machine (9); a polarization block (14) with a first input (15) connected to the output of the first digital-analog converter (12) and a second input (16) connected to the output of the second digital-analog converter (13); where the polarization block (14) polarizes an electronic circuit (17) and the dynamic comparator (1), the phase detector (6), and the finite-state machine (9) are connected to a clock signal (3). The method is characterized by the following steps: a) connecting a dynamic comparator to the output of the electronic circuit; b) measuring the phase change of the dynamic comparator outputs of step a by means of a phase detector; c) controlling the output signals of a finite-state machine according to the phase detector output of step b, which can be coded forward, backward or in phase; c) converting the output of the finite-state machine of step c to an analog signal using two digital-analog converters; d) connecting the output of the two digital-analog converters of step d to the control terminal of the electronic circuit polarization block; and, e) modifying the polarization current of the electronic circuit polarization block by means of the output signals of the two digital-analog converters connected in step e.

Disclosed is a high accurate measurement circuit, and the feature is using bias switching circuit for compensating front end offset, and the back end offset of amplifier is also cancelled. In the real measurement environment, offset exists in the amplifier of the measurement circuit has, and non-ideal effects also exist in the interface between measurement terminal and the measurement circuit, such as leakage current of chip package pins or mismatch of the circuit. The above non-ideal effects belong to front end offset and cannot be compensated by the prior arts. The disclosed structure uses the bias switch circuit and uses different switching method in the two measurement timings. By subtracting the measurement results for the two measurement timings, the front end offset is compensated, and the back end offset of the amplifier is also cancelled.

A feedback stage for an integrator circuit is provided. The integrator receives a first input current and a second input current that include respective measurement current components and an offset current component. The integrator integrates the first input current and the second input current and generates a first output voltage and a second output voltage. The feedback stage including a transconductance amplifier detects a difference between the first output voltage and the second output voltage and sinks or sources a first output current and a second output current based on the difference between the first output voltage and the second output voltage. The first output current is additively combined with the first input current and the second output current is additively combined with the second input current to mitigate the offset current component at an input of the integrator.

A current sensing amplifier circuit includes: an amplifier configured to generate an output voltage correlated with a current to-be-sensed according to a first input voltage at a first input end and a second input voltage at a second input end in a normal operation mode; and a current source circuit configured to generate a trimming current according to the first input voltage and a reference voltage in a trimming mode and to provide the trimming current to trim an offset referred to input (RTI) voltage generated by the current sensing amplifier circuit in the normal operation mode. The current source circuit is coupled between: a first resistor and a non-inverting input end, a second resistor and the output voltage, a third resistor and the non-inverting input end, or a fourth resistor and an inverting input end.

A differential circuit including: a first MOS transistor and a second MOS transistor that constitute a differential pair; a determination unit to determine a level of a determination target signal that is based on at least one of differential inputs being input to gate of the first MOS transistor and a gate of the second MOS transistor; and a voltage changing unit to change a back gate voltage that is supplied to both back gates of the first MOS transistor and the second MOS transistor according to a determination result of the determination unit, and an OP-amp will be provided.

A semiconductor amplifier circuit comprising an input block adapted for receiving a voltage signal to be amplified, an integrator circuit having an integrating capacitor providing a continuous-time signal representative for the integral of the voltage signal, a first feedback path comprising: a sample-and-hold block and a first feedback block, the first feedback path providing a proportional feedback signal upstream of the current integrator. The amplification factor is larger than 1 for a predefined frequency range. Charge stored on the integrating capacitor at the beginning of a sample period is linearly removed during one single sampling period in such a way that the absolute value of the charge is smaller at the end of the sampling period than at the beginning of the sample period when the voltage signal to be amplified is equal to zero.

A differential circuit including: a first MOS transistor and a second MOS transistor that constitute a differential pair; a determination unit to determine a level of a determination target signal that is based on at least one of differential inputs being input to gate of the first MOS transistor and a gate of the second MOS transistor; and a voltage changing unit to change a back gate voltage that is supplied to both back gates of the first MOS transistor and the second MOS transistor according to a determination result of the determination unit, and an OP-amp will be provided.