According to an aspect, an auto-zero amplifier includes a main amplifier, a secondary amplifier connected to the main amplifier, a plurality of switching including a first switch and a second switch, and a leakage control circuit.

A receiver includes a first T-coil circuit at an input of the receiver and configured to receive an input signal, a termination impedance coupled to the first T-coil circuit and configured to match an impedance of a transmission line coupled to the first T-coil circuit, and an amplifier including a first input and a second input and configured to amplify a differential signal at the first and second inputs, a calibration switch coupled to the amplifier and configured to selectively electrically connect or disconnect the first and second inputs of the amplifier, and a first receive switch configured to selectively electrically connect or disconnect a center node of the first T-coil circuit and the amplifier.

A fast-locking phase-locked loop (PLL) and an associated fast-locking method thereof are provided. The fast-locking PLL may include a gear-shifting loop filter, which is configured to have a dynamic bandwidth. The gear-shifting loop filter may include a resistor set and a capacitor set coupled to the resistor set, where the resistor set is configured to have a dynamic resistance, and the capacitor set is configured to have a dynamic capacitance. More particularly, the dynamic resistance is switched from a first resistance to a second resistance and the dynamic capacitance is switched from a first capacitance to a second capacitance, to make the dynamic bandwidth be switched from a first bandwidth to a second bandwidth.

A system and method for operating a sensing circuit for sensing a pixel current of a pixel of a display panel using correlated double sampling. In some embodiments, the method includes: during a first interval of time, resetting a pixel sensing circuit; during a third interval of time following the first interval of time, operating the pixel sensing circuit in an integration mode; during a fourth interval of time following the third interval of time, operating the pixel sensing circuit in a hold mode; and during a fifth interval of time following the fourth interval of time, operating the pixel sensing circuit in the integration mode.

According to an aspect, an auto-zero amplifier includes a main amplifier, a secondary amplifier connected to the main amplifier, a plurality of switching including a first switch and a second switch, and a leakage control circuit.

The first and second input terminals are configured to receive first and second current signal respectively. The first FET has a first current terminal electrically connected to the first input terminal, a second current terminal electrically connected to the second input terminal, and a first control terminal receiving a first control signal. The first TIA circuit has a first input node which is electrically connected to the first current terminal. The first TIA circuit converts a current signal received at the first input node to the first voltage signal. The second TIA circuit has a second input node which is electrically connected to the second current terminal. The second TIA circuit converts a current signal received at the second input node to the second voltage signal. The control circuit generates the first control signal in accordance with a difference between the first and second voltage signals.

This disclosure describes auto-zero amplifier circuit that include an additional capacitor (or other capacitive component) that can be switchably coupler to a reference voltage. The auto-zero amplifier circuit can generate an auto-zero compensation signal using a difference between the reference voltage stored on the additional capacitor and a voltage stored on another auto-zero capacitor.

A system has an output and receives an input signal. An operational amplifier has an input, an output and an offset at the input. A switched capacitor network samples the input signal at a switched capacitor frequency. An autozeroing capacitor connected to the input of the operational amplifier captures the offset during an offset capture interval according to an autozeroing frequency. Chopping and autozeroing switches, connected between the autozeroing capacitor and the switched capacitor network, chop the sampled input signal according to a chopping frequency and autozero the captured offset according to the autozeroing frequency. De-chopping switches, connected between the output of the operational amplifier and the output of the system, operate on the output of the operational amplifier at the chopping frequency to chop the autozeroed captured offset and de-chop the chopped sampled input signal processed by the operational amplifier.

A signal error calibrating method is disclosed herein and includes following steps: filtering an error voltage in a sensor by a low pass filter in a calibration mode; converting the offset voltage to be a digital offset signal by an analog digital signal converter; converting the digital offset signal to be an offset calibrating signal by a digital analog signal converter; transmitting the offset calibrating signal to an input end of the sensor so as to offset an error voltage at the input end of the sensor. After calibrating the error voltage, the analog digital converter in the error calibrating circuit can be used for the need of signal output and the low pass filter is turned off at the same time.

A system and method for operating a sensing circuit for sensing a pixel current of a pixel of a display panel using correlated double sampling. In some embodiments, the method includes: during a first interval of time, resetting a pixel sensing circuit; during a third interval of time following the first interval of time, operating the pixel sensing circuit in an integration mode; during a fourth interval of time following the third interval of time, operating the pixel sensing circuit in a hold mode; and during a fifth interval of time following the fourth interval of time, operating the pixel sensing circuit in the integration mode.