A current sensing amplifier circuit includes: an amplifier configured to generate an output voltage correlated with a current to-be-sensed according to a first input voltage at a first input end and a second input voltage at a second input end in a normal operation mode; and a current source circuit configured to generate a trimming current according to the first input voltage and a reference voltage in a trimming mode and to provide the trimming current to trim an offset referred to input (RTI) voltage generated by the current sensing amplifier circuit in the normal operation mode. The current source circuit is coupled between: a first resistor and a non-inverting input end, a second resistor and the output voltage, a third resistor and the non-inverting input end, or a fourth resistor and an inverting input end.

A sensor circuit may include one or more feedback loops to process and attenuate ripple and/or a test signal. The sensor circuit may comprise at least one magnetic field sensing element to generate a magnetic field signal representing a magnetic field to be measured, a test signal generator circuit configured to generate a test signal and combine the test signal with the magnetic field signal to generate a combined signal, and a signal path for processing the combined signal. The signal path may comprise an amplifier circuit to amplify the combined signal, an analog-to-digital converter (ADC) to convert the combined signal to a digital combined signal, and a feedback circuitry coupled to receive the digital combined signal and extract the test signal. A test comparator circuit compares the extracted test signal to a reference signal.

A circuit and method in an amplifier circuit for filtering a DC offset in differential input signals and inserting a programmable adjustable crosspoint offset in differential output signals. An amplifier circuit includes a differential amplifier circuit configured to amplify differential input signals into differential output signal. The amplifier circuit further includes a feedback circuit coupled between the differential output signals and the differential input signals. The feedback circuit is configured to generate a programmably adjustable crosspoint offset in the differential output signal and a programmably adjustable cutoff frequency of the feedback circuit. An amplifier method includes amplifying differential input signals into differential output signals, generating a programmably adjustable crosspoint offset in the differential output signal, and generating a programmably adjustable cutoff frequency of a feedback circuit between the differential output signals and the differential input signals.

Single controller automatic calibrating circuits for reducing or canceling offset voltages in operational amplifiers (op-amps) in an instrumentation amplifier are disclosed. An automatic calibrating op-amp system is provided that includes an instrumentation amplifier, which includes a front-end amplifier circuit comprising at least one front-end op-amp and a final-stage amplifier circuit comprising a final-stage op-amp. The op-amp(s) can include auxiliary differential inputs for offset voltage cancellation. The automatic calibrating op-amp system also includes an automatic calibration circuit employing a single controller to generate calibration signals on a calibration output to an auxiliary differential input(s) of an op-amp(s) in the instrumentation amplifier for offset voltage cancellation. The automatic calibration circuit includes a single controller to generate calibration signals to the instrumentation amplifier to reduce or cancel offset voltage, thereby eliminating the need to provide multiple automatic calibration circuits or an automatic calibration circuit employing multiple controllers.

A signal error calibrating method is disclosed herein and includes following steps: filtering an error voltage in a sensor by a low pass filter in a calibration mode; converting the offset voltage to be a digital offset signal by an analog digital signal converter; converting the digital offset signal to be an offset calibrating signal by a digital analog signal converter; transmitting the offset calibrating signal to an input end of the sensor so as to offset an error voltage at the input end of the sensor. After calibrating the error voltage, the analog digital converter in the error calibrating circuit can be used for the need of signal output and the low pass filter is turned off at the same time.

To provide a variable reference voltage source for which a measuring instrument is unnecessary for calibration on the outside. A variable reference voltage source that generates a variable reference voltage corresponding to setting data set from outside includes a control unit including a calibration control unit that controls operation for calibrating an offset and a predetermined unit voltage inside the variable reference voltage source and an output control unit that controls operation for outputting the variable reference voltage, a reference voltage unit that outputs a reference voltage Vref, and an integrated-voltage generating unit that repeats, when the calibration control unit controls the operation, an integrating operation until an integrated voltage obtained by integrating the predetermined unit voltage becomes equal to the reference voltage Vref and outputs, when the output control unit controls the operation, the variable reference voltage corresponding to the setting data.

An analog circuit including a pair of input nodes and a pair of output nodes is coupled to a mismatch reduction circuit including an input node, an output node, a phase controller that times even and odd phases, an input switch, and an output switch. The input switch electrically connects the mismatch reduction circuit input node to a first node of the pair of analog circuit input nodes during each even phase and to electrically connects the mismatch reduction circuit input node to a second node of the pair of analog circuit input nodes during each odd phase. The output switch electrically connects a first node of the pair of analog circuit output nodes to the mismatch reduction circuit output node during each even phase and electrically connects a second node of the pair of analog circuit output nodes to the mismatch reduction circuit output node during each odd phase.

An apparatus includes an amplifier, an input port, a first modulator circuit connected to the input port, and a correction circuit. The correction circuit is configured to determine a common mode voltage of the input port and receive a first clock signal. The correction circuit is further configured to manipulate, based at least in part upon the common mode voltage of the input port, the first clock signal to generate a second clock signal. The second clock signal is produced for the first modulator circuit. The correction circuit is further configured to determine whether the second clock signal is out of phase with a third clock signal, and, based upon a determination that the second clock signal is out of phase with the third clock signal, reset the second clock signal.

Apparatus and associated methods relate to a peaking module fabricated on a semiconductor substrate including a follower circuit driving a series peaking circuit-branch, the module configured to extend the bandwidth of a track-and-hold circuit. In an illustrative example, the series peaking circuit-branch may include an inductive element. One or more tracks on a metal interconnect above the semiconductor substrate may form the inductive element, for example. In some examples, one or more peaking modules may be combined creating a customized frequency response. In some examples, one or more combined peaking modules may be adjusted by a controller providing dynamic frequency response customization during operation. The follower circuits may employ constant current biasing and/or constant-g.sub.m biasing to provide substantial immunity to process, temperature and voltage variations, for example. Various implementations of series peaking circuit-branch pre-emphasis may advantageously extend overall bandwidth of various circuits (e.g., high-speed track-and-hold circuits).

A circuit and method in an amplifier circuit for filtering a DC offset in differential input signals and inserting a programmable adjustable crosspoint offset in differential output signals. An amplifier circuit includes a differential amplifier circuit configured to amplify differential input signals into differential output signal. The amplifier circuit further includes a feedback circuit coupled between the differential output signals and the differential input signals. The feedback circuit is configured to generate a programmably adjustable crosspoint offset in the differential output signal and a programmably adjustable cutoff frequency of the feedback circuit. An amplifier method includes amplifying differential input signals into differential output signals, generating a programmably adjustable crosspoint offset in the differential output signal, and generating a programmably adjustable cutoff frequency of a feedback circuit between the differential output signals and the differential input signals.