A regulator includes an operational amplifier, a programmable offset voltage, and a circuit. The operational amplifier includes a non-inverting input, an inverting input, and an output. The programmable offset voltage is configured to cancel a built-in offset voltage of the regulator based on a code. The circuit is configured to set the code based on a sensed built-in offset voltage of the regulator in response to an offset cancellation calibration mode enable signal.

Apparatus for performing offset cancellation is disclosed. The apparatus comprises a gating circuit (6) for receiving an analogue signal (3) from a source (2) and providing a gated analogue signal (9) to an analogue circuit (10), a gating controller (7; 14; FIG. 1) and a digital processor (14; FIG. 1) for receiving a digital signal (13) converted from an analogue output (11) from the analogue circuit (10). The gating circuit comprises at least one path (21.sub.1), each path respectively comprising, an input terminal (22.sub.1), an output terminal (23.sub.1), a node (24.sub.1) interposed between the input and output terminals, a first transistor (Q1) having a channel arranged between the input terminal and the node, and a second transistor (Q3) having channel arranged between the node and a fixed reference, such as ground (GND). The gating controller is configured, in a first time window (15.sub.A), to switch the first transistor so that the input terminal and the output terminal are decoupled and to switch the second transistor so that the node is coupled to the fixed reference. The gating controller is configured, in a second, different time window (15.sub.B), to switch the second transistor so that the node and the fixed reference are decoupled and to switch the first transistor so that the input terminal is coupled to the input terminal. The digital processor is configured, in the first time window, to take a first measurement of the digital signal, and, in the second, different time window, to take a second measurement of the digital signal. The digital processor configured to subtract the first measurement from the second measurement.

Embodiments relate to sensing a current provided by a power supply circuit. The current sensing circuit includes a sense transistor for sensing the current provided by a main transistor, a driver for controlling a bias provided to the sense transistor and the main transistor, and a sense resistor for converting the sensed current to a voltage value. Moreover, the current sensing circuit includes a controller that modifies at least one of: (a) a resistance of the main transistor by adjusting the bias voltage provided by the driver, (b) a gain ratio between a load current and a sensing current by adjusting a number of individual devices that are active in the sense transistor, and (c) a resistance of the sense resistor.

In a general aspect, a circuit can include an input circuit configured to receive an input signal, and an amplifier circuit coupled with the input circuit. The amplifier circuit can include an amplifier, and first and second feedback paths. The first feedback path can be from a positive output to a negative input of the amplifier, and the second feedback path can be from a negative output to a positive input of the first amplifier. The circuit can also include a loop circuit configured to provide a local feedback loop for the first amplifier and configured to control current flow into the positive input of the first amplifier and current flow into the negative input of the first amplifier. The circuit can also include a control circuit that is configured to enable the loop circuit in response to a magnitude of the input signal exceeding a threshold.

A regulator includes an operational amplifier, a programmable offset voltage, and a circuit. The operational amplifier includes a non-inverting input, an inverting input, and an output. The programmable offset voltage is configured to cancel a built-in offset voltage of the regulator based on a code. The circuit is configured to set the code based on a sensed built-in offset voltage of the regulator in response to an offset cancellation calibration mode enable signal.

An analog to digital converter (ADC) includes a conversion circuit digitizing an input analog signal to produce an output digital signal. A current generator generates a constant bias current. A current mirror circuit includes an input transistor receiving the constant bias current, an output transistor in a mirroring relationship with the input transistor and generating a variable bias current, and a parallel transistor circuit selectively coupling a parallel transistor in parallel with the input transistor or the output transistor in response to a control signal. The control signal is representative of the conversion rate of the ADC. A buffer generates a common mode voltage for use by the conversion circuit, from the variable bias current.

Embodiments relate to sensing a current provided by a power supply circuit. The current sensing circuit includes a sense transistor for sensing the current provided by a main transistor, a driver for controlling a bias provided to the sense transistor and the main transistor, and a sense resistor for converting the sensed current to a voltage value. Moreover, the current sensing circuit includes a controller that modifies at least one of: (a) a resistance of the main transistor by adjusting the bias voltage provided by the driver, (b) a gain ratio between a load current and a sensing current by adjusting a number of individual devices that are active in the sense transistor, and (c) a resistance of the sense resistor.

A preamplifier comprises an input stage and a capacitive coupling stage. The input stage is arranged to receive a differential signal from a magnetic resistor which indicates a magnetic field sensed on a magnetic disk of a hard disk drive (HDD) when the preamplifier is powered on from an off state. The capacitive coupling stage has an input arranged to receive the differential signal from the input stage, a filter comprising a first resistor, a second resistor, a first capacitor, a second capacitor, and switches arranged in parallel with respective resistors, where the switches are closed when the preamplifier is powered on from the off state to an on state. A switch control is arranged to determine that an offset of the differential signal has settled and open the switches based on the determination.

Embodiments described herein include radio frequency (RF) switches. In general, the embodiments described herein selectively bias the output terminals of one or more switching transistors in the RF switch. Such coupling can provide a bias that significantly reduces the effects of gate-lag. In one embodiment, the RF switch includes an antenna node, a first input/output (I/O) node, a second I/O node, a field-effect transistor (FET), a FET stack, and a bias coupling circuit. In this embodiment the bias coupling circuit electrically couples a gate terminal of the FET to one or more FET output terminals of the FET stack to provide a bias voltage to the output terminal(s).

Apparatus for performing offset cancellation is disclosed. The apparatus comprises a gating circuit (6) for receiving an analogue signal (3) from a source (2) and providing a gated analogue signal (9) to an analogue circuit (10), a gating controller (7; 14; FIG. 1) and a digital processor (14; FIG. 1) for receiving a digital signal (13) converted from an analogue output (11) from the analogue circuit (10). The gating circuit comprises at least one path (21.sub.1), each path respectively comprising, an input terminal (22.sub.1), an output terminal (23.sub.1), a node (24.sub.1) interposed between the input and output terminals, a first transistor (Q1) having a channel arranged between the input terminal and the node, and a second transistor (Q3) having channel arranged between the node and a fixed reference, such as ground (GND). The gating controller is configured, in a first time window (15.sub.A), to switch the first transistor so that the input terminal and the output terminal are decoupled and to switch the second transistor so that the node is coupled to the fixed reference. The gating controller is configured, in a second, different time window (15.sub.B), to switch the second transistor so that the node and the fixed reference are decoupled and to switch the first transistor so that the input terminal is coupled to the input terminal. The digital processor is configured, in the first time window, to take a first measurement of the digital signal, and, in the second, different time window, to take a second measurement of the digital signal. The digital processor configured to subtract the first measurement from the second measurement.