In accordance with an embodiment, a method includes receiving a first differential logic signal using a first branch of a circuit that extends from a voltage supply of the circuit as far as an earth terminal of the circuit and has at least one first differential transistor pair, receiving a second differential logic signal using a second branch of the circuit that extends from the voltage supply to the earth terminal and has at least one second differential transistor pair, conducting a current flow between the first branch and the second branch, and outputting an output signal by the second branch.

A latch circuit providing isolated input current paths includes a pair of input transistors that receive a differential input signal. A plurality of steering transistors receive a portion of a differential clock signal. The latch circuit includes a positive output node and a negative output node. A first bypass input current path is associated with the first input transistor and is electrically isolated from the positive output node and the negative output node. A second bypass input current path associated with the second input transistor is also electrically isolated from the positive output node and the negative output node. In a latched state, the clock signal is operative to selectively bias the plurality of steering transistors such that current is steered to one of the first input current path or the second input current path, thereby being isolated from the output nodes.

A latch circuit providing isolated input current paths includes a pair of input transistors that receive a differential input signal. A plurality of steering transistors receive a portion of a differential clock signal. The latch circuit includes a positive output node and a negative output node. A first bypass input current path is associated with the first input transistor and is electrically isolated from the positive output node and the negative output node. A second bypass input current path associated with the second input transistor is also electrically isolated from the positive output node and the negative output node. In a latched state, the clock signal is operative to selectively bias the plurality of steering transistors such that current is steered to one of the first input current path or the second input current path, thereby being isolated from the output nodes.

Techniques are disclosed for a level shifter configured to adjust current flow in response to measured current fluctuations due to common mode noise in the level shifter. For example, the level shifter includes a low-side control circuit configured to adjust a first current flowing into a first low-side terminal of an active high voltage level shifter device in response to a difference between the first low-side current and a second low-side current flowing into a second low-side terminal of an inactive high voltage level shifter device. The level shifter further includes a high-side receiver circuit configured to detect a difference between a first high-side current flowing into a first high-side terminal of the active high voltage level shifter device and a second high-side current flowing into a second high-side terminal of the inactive high voltage level shifter device.

Techniques are disclosed for a level shifter configured to adjust current flow in response to measured current fluctuations due to common mode noise in the level shifter. For example, the level shifter includes a low-side control circuit configured to adjust a first current flowing into a first low-side terminal of an active high voltage level shifter device in response to a difference between the first low-side current and a second low-side current flowing into a second low-side terminal of an inactive high voltage level shifter device. The level shifter further includes a high-side receiver circuit configured to detect a difference between a first high-side current flowing into a first high-side terminal of the active high voltage level shifter device and a second high-side current flowing into a second high-side terminal of the inactive high voltage level shifter device.

Techniques are disclosed for a level shifter configured to adjust current flow in response to measured current fluctuations due to common mode noise in the level shifter. For example, the level shifter includes a low-side control circuit configured to adjust a first current flowing into a first low-side terminal of an active high voltage level shifter device in response to a difference between the first low-side current and a second low-side current flowing into a second low-side terminal of an inactive high voltage level shifter device. The level shifter further includes a high-side receiver circuit configured to detect a difference between a first high-side current flowing into a first high-side terminal of the active high voltage level shifter device and a second high-side current flowing into a second high-side terminal of the inactive high voltage level shifter device.