A regeneration circuit includes a first inverting circuit, a second inverting circuit, a first transistor coupled to an input of the second inverting circuit, and a second transistor coupled to an input of the first inverting circuit. The regeneration circuit also includes a third transistor including a gate coupled to a gate of the first transistor, a first switch configured to couple the third transistor to the input of the second inverting circuit based on a voltage of the first inverting circuit, a fourth transistor including a gate coupled to a gate of the second transistor, and a second switch configured to couple the fourth transistor to the input of the first inverting circuit based on a voltage of the second inverting circuit.

Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a programmable logic device (PLD) includes a plurality of programmable logic blocks (PLBs) and at least first and second logic cells within at least one of the PLBs, where each logic cell includes a lookup table (LUT) and associated mode logic configured to receive a LUT output signal from the LUT. The associated mode logic is configured to use a single physical signal output to provide a logic cell output signal corresponding to a selected logic function operational mode, ripple arithmetic operational mode, or extended logic function operational mode for each logic cell.

A semiconductor device includes: single-bit flip-flop regions (SBFF regions) which comprise a multi-bit flip-flop (MBFF) region; the MBFF region having a two-dimensional floor plan represented by a grid including rows and a first column extending in corresponding first and perpendicular second directions, each SBFF region representing an intersection of a corresponding row and column; the SBFF regions being coupled in a daisy chain for which an output of a preceding one of the SBFF regions in the daisy chain is coupled to an input of a succeeding one of the SBFF regions in the daisy chain; and orientations of the SBFF regions relative to the first direction (?-orientations) being arranged in an alternating pattern relative to the second direction so that a two-dimensional representation of a flow path of a data signal along the first column has a serpentine shape.

A semiconductor device includes a first active region, a second active region, a first gate line disposed to overlap the first and second active regions, a second gate line disposed to overlap the first and second active regions, a first metal line electrically connecting the first and second gate lines and providing a first signal to both the first and second gate lines, a first contact structure electrically connected to part of the first active region between the first and second gate lines, a second contact structure electrically connected to part of the second active region between the first and second gate lines, and a second metal line electrically connected to the first and second contact structures and transmitting a second signal, wherein an overlapped region that is overlapped by the second metal line does not include a break region.

Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a programmable logic device (PLD) includes a plurality of programmable logic blocks (PLBs) and at least first and second logic cells within at least one of the PLBs, where each logic cell includes a lookup table (LUT) and associated mode logic configured to receive a LUT output signal from the LUT. The associated mode logic is configured to use a single physical signal output to provide a logic cell output signal corresponding to a selected logic function operational mode, ripple arithmetic operational mode, or extended logic function operational mode for each logic cell.

At least some embodiments are directed to a flip-flop that comprises a tri-state inverter and a master latch coupled to the tri-state inverter and comprising a first transistor, a first inverter, and a first logic gate. The master latch receives a clock signal. The flop also comprises a slave latch coupled to the master latch and comprising a second transistor and a second inverter. The slave latch receives the clock signal. The flop further comprises an enablement logic coupled to the master latch and comprising multiple, additional logic gates. The tri-state inverter, the master and slave latches, and the enablement logic are configured so that when a flip-flop input signal D and a flip-flop output signal Q are identical and the clock signal is toggled, a state of the master latch and a state of the slave latch remain static.

First and second active regions are doped with different types of impurities, and extend in a first direction and spaced apart from each other in a second direction. First and third gate structures, which are on the first active region and a first portion of the isolation layer between the first and second active regions, extend in the second direction and are spaced apart from each other in the first direction. Second and fourth gate structures, which are on the second active region and the first portion, extend in the second direction, are spaced apart from each other in the first direction, and face and are spaced apart from the first and third gate structures, respectively, in the second direction. First to fourth contacts are on portions of the first to fourth gate structures, respectively. The first and fourth contacts are connected, and the second and third contacts are connected.

A semiconductor device includes a first active region, a second active region, a first gate line disposed to overlap the first and second active regions, a second gate line disposed to overlap the first and second active regions, a first metal line electrically connecting the first and second gate lines and providing a first signal to both the first and second gate lines, a first contact structure electrically connected to part of the first active region between the first and second gate lines, a second contact structure electrically connected to part of the second active region between the first and second gate lines, and a second metal line electrically connected to the first and second contact structures and transmitting a second signal, wherein an overlapped region that is overlapped by the second metal line does not include a break region.

At least some embodiments are directed to a flip-flop that comprises a tri-state inverter and a master latch coupled to the tri-state inverter and comprising a first transistor, a first inverter, and a first logic gate. The master latch receives a clock signal. The flop also comprises a slave latch coupled to the master latch and comprising a second transistor and a second inverter. The slave latch receives the clock signal. The flop further comprises an enablement logic coupled to the master latch and comprising multiple, additional logic gates. The tri-state inverter, the master and slave latches, and the enablement logic are configured so that when a flip-flop input signal D and a flip-flop output signal Q are identical and the clock signal is toggled, a state of the master latch and a state of the slave latch remain static.

Embodiments include apparatuses, methods, and systems for a flip-flop circuit with low-leakage transistors. The flip-flop circuit may be coupled to a logic circuit of an integrated circuit to store data for the logic circuit when the logic circuit is in a sleep state. The flip-flop circuit may pass a data signal for the logic circuit along a signal path. A capacitor may be coupled between the signal path and ground to store a value of the data signal when the logic circuit is in the sleep state. A low-leakage transistor, such as an IGZO transistor, may be coupled between the capacitor and the signal path and may selectively turn on when the logic circuit transitions from the active state to the sleep state to store the value of the data signal in the capacitor. Other embodiments may be described and claimed.