Disclosed is a charge-pump phase-locked loop based on a unipolar thin film transistor, a chip, and a method. The phase-locked loop may include: a phase-frequency detector, configured to detect a phase difference and a frequency difference between a clock F.sub.ref and a clock F.sub.n and generate control signals UP and DOWN; a logic control module, configured to output logic state signals; a charge pump, configured to convert the logic state signals into a charging/discharging current signal; a low-pass filter, configured to output a direct-current analog control signal V.sub.ctrl; a voltage-controlled oscillator, configured to adjust an output clock frequency F.sub.vco; and a divide-by-four circuit, configured to perform frequency division to obtain the clock F.sub.n.

A phase locked loop having a charge pump is described. The charge pump has circuitry to select a mode for each semiconductor chip from a plurality of modes to enhance yield. Nine unique modes are defined from which a selection is made for each chip. The selected mode mitigates effects of device mistracking anomalies for each chip. A method is provided to show how the modes are determined and prioritized.

Multi-mode non-return-to-zero (NRZ) and orthogonal differential vector signaling (ODVS) clock and data recovery circuits having configurable sub-channel multi-input comparator (MIC) circuits for forming a composite phase-error signal from a plurality of data-driven phase-error signals generated using phase detectors in a plurality of receivers configured as ODVS sub-channel MICs generating orthogonal sub-channel outputs in a first mode and a separate first and second data driven phase-error signal from two receivers of a plurality of receivers configured as NRZ receivers in a second mode.

A delay locked loop circuit includes a first delay locked loop and a second delay locked loop having different characteristics. The first delay locked loop performs a delay-locking operation on a reference clock signal to generate a delay locked clock signal. The second delay locked loop performs a delay-locking operation on the delay locked clock signal to generate an internal clock signal.

A charge pump includes: (I) a current source; (II) a p-channel source current network including: a first p-channel transistor; a second p-channel transistor; a p-channel current switch including at least one source terminal coupled to the drain terminal of the first p-channel transistor, at least one gate coupled to a phase comparator, and at least one drain terminal; a third p-channel transistor; and (III) a n-channel sink current network including: a first n-channel transistor; a second n-channel transistor; a third n-channel transistor; a n-channel current switch comprising at least one drain terminal coupled to the source terminal of the third n-channel transistor, at least one gate coupled to the phase comparator; and at least one source terminal coupled to the drain terminal of the first n-channel transistor; and wherein the p-channel source current network and the n-channel sink current network draw a baseline current from the first p-channel transistor.

There is configured a charge pump circuit for outputting a phase difference current to a first node, the charge pump circuit including a first current source coupled between a high potential power supply node and the first node, a second current source coupled between a low potential power supply node and the first node, a first switch coupled between the first current source and the first node, a second switch coupled between the second current source and the first node, a third switch coupled between the first current source and a second node, a fourth switch coupled between the second current source and the second node, a third current source for supplying a negative offset current to the first node, and a push-type differential amplifier circuit an input side of which is coupled to the first node, and an output side of which is coupled to the second node.

A charge pump includes: a switch circuit that switches a current source conducted to an output node based on a signal from a phase frequency detector included in a PLL circuit; a first current source that is the current source provided between a high potential node and the switch circuit, and supplies a current to the output node by a first conduction-type depletion mode MOS transistor forming a self-bias circuit; and a second current source that is the current source provided between a low potential node and the switch circuit, and draws the current from the output node by the first conduction-type depletion mode MOS transistor forming the self-bias circuit.

The present technology relates to a charge pump circuit that enables reduction of a circuit area. Provided is a charge pump circuit including: a first transistor; a second transistor to which a constant current is supplied; a third transistor connected to the first transistor and a voltage source; a fourth transistor group including N transistors arranged in a cascade on the first transistor side, the N transistors all including control terminals connected to the second transistor; a fifth transistor group including N transistors arranged in a cascade on the second transistor side, the N transistors all including control terminals connected to the second transistor; a first switch that connects the first transistor to the second transistor; a second switch that connects the first transistor to a ground node; a third switch that connects the third transistor to the fifth transistor group; and a fourth switch that connects the third transistor to the ground node.

The present technology relates to a charge pump circuit that enables reduction of a circuit area.

Provided is a charge pump circuit including: a first transistor; a second transistor to which a constant current is supplied; a third transistor connected to the first transistor and a voltage source; a fourth transistor group including N transistors arranged in a cascade on the first transistor side, the N transistors all including control terminals connected to the second transistor; a fifth transistor group including N transistors arranged in a cascade on the second transistor side, the N transistors all including control terminals connected to the second transistor; a first switch that connects the first transistor to the second transistor; a second switch that connects the first transistor to a ground node; a third switch that connects the third transistor to the fifth transistor group; and a fourth switch that connects the third transistor to the ground node.

A delay locked loop circuit includes a first delay locked loop and a second delay locked loop having different characteristics. The first delay locked loop performs a delay-locking operation on a reference clock signal to generate a delay locked clock signal. The second delay locked loop performs a delay-locking operation on the delay locked clock signal to generate an internal clock signal.