An apparatus includes a phase-locked loop (PLL) circuit and a logic circuit. The logic circuit may manage, via one or more programmable operating parameters of the PLL circuit, PLL bandwidth variation exhibited by the PLL circuit due to variations in its manufacturing process (P), supply voltage (V) or temperature (T), i.e., PVT variations exhibited by the PLL circuit.

The present disclosure relates to a phase-locked loop circuit and a signal processing device. The phase-locked loop circuit includes: a charge pump configured with a charge pump current; and a loop filter connected to the charge pump and configured with a first resistance value, a first capacitance value, and a second capacitance value, wherein a zero frequency of the phase-locked loop circuit is configured to be determined by the first resistance value and the first capacitance value, and a pole frequency of the phase-locked loop circuit is configured to be determined by the first resistance value and the second capacitance value; wherein at least two of the charge pump current, the first resistance value, the first capacitance value, and the second capacitance value are adjustable, to change a loop bandwidth of the phase-locked loop circuit, to maintain a first ratio between the zero frequency and the loop bandwidth unchanged, and to maintain a second ratio between the pole frequency and the loop bandwidth unchanged.

A technique for reducing effects of variations in process, voltage, and temperature (PVT) on the performance of a fractional-N frequency synthesizer includes making loop parameters, e.g., damping factor and loop bandwidth .sub.N, first-order independent of PVT variations. In an embodiment of a fractional-N frequency synthesizer, a voltage-controlled oscillator is implemented using a ring-oscillator realized by an odd number of inverter stages. By making the loop parameters a multiple of frequency f.sub.REF and a ratio of components (e.g., C.sub.1/C.sub.st, where capacitance C.sub.st represents the load of each stage of the ring oscillator) and self-biasing the phase-locked loop, the technique makes the ratio of loop bandwidth .sub.n to the operating frequency f.sub.CLKOUT constant in response to PVT variations.

A technique for reducing the effects of charge injection when a charge pump in a fractional-N frequency synthesizer switches from an error cancellation phase of error current generation to a full-scale phase of error current generation uses a dummy digital-to-analog converter to steer excess current from the error cancellation phase to a voltage regulated node. As a result, the voltage swing of an inactive branch of a digital-to-analog converter of the charge pump is the same as the voltage swing of the active branch of the charge pump, i.e., the device overlap capacitance charge injection is in phase for the branches of a digital-to-analog converter in the charge pump.

Provided is a semiconductor device that suppresses an increase in an area and current of a PLL. An ADPL and an SPLL are included, and an SPD that compares an input signal with a feedback signal from a CCO, a charge pump circuit that outputs a current or a voltage based on a result of the SPD, a PFD that detects a phase difference which is a comparison result between the input signal and the feedback signal, and a phase difference digitizer that changes the current output by the charge pump circuit based on a detection result of the PFD are included.