A signal processing circuit includes a filter generating a quantizer input signal from a noise shaping input signal and a quantizer output signal. A quantizer divides the quantizer input signal by a scaling factor to produce a noise shaping output signal and multiplies the noise shaping output signal by the scaling factor to produce the quantizer output signal. Receiver circuitry scales the quantizer output signal by a second scaling factor. A dynamic range optimization circuit compares a current value of the noise shaping input signal to a threshold value, lowers or raises the scaling factor in response to the comparison, and proportionally lowers or raises the scaling factor such that a ratio between the scaling factor and second scaling factor remains substantially constant.

A low-pass and band-pass delta-sigma (??) analog-to-digital converter (ADC) device for sensor interface is disclosed. The device includes a first stage comprising a low-resolution passive integrator-based noise-shaping successive approximation register (SAR) ADC and a second stage comprising a voltage-controlled oscillator (VCO)-ADC.

The present application provides a vector quantization digital-to-analog conversion circuit, applied to an oversampling converter, characterized that the vector quantization digital-to-analog conversion circuit comprises a vector quantization circuit, configured to generate a vector quantization signal, a data weighted averaging circuit, coupled to the vector quantization circuit, comprising a plurality of data weighted averaging sub-circuits, configured to receive the vector quantization signal to generate a plurality of data weighted averaging signals; and a digital-to-analog conversion circuit, coupled to the data weighted averaging circuit, comprising a plurality of digital-to-analog conversion sub-circuits, configured to receive the data weighted averaging signal to generate the analog signal.

Radar frequency range signals (e.g., 1 to 100 gigahertz) are often generated by upconverting a reference frequency to a transmission frequency, and a received signal may be downconverted to analyze information encoded on the transmission via modulation. Modulation may be achieved via a fractional frequency divider in a phase-locked loop, but fractional spurs may reduce the signal-to-noise ratio. Additionally, the ramp slope may vary due to phase-locked loop momentum. Instead, a clock generator may generate clock signals for a digital front end comprising a digital signal modulator that generates modulated digital values comprising quadrature representations of a radar modulation signal, which are encoded by a radiofrequency digital-to-analog converter (RF-DAC). The RF-DAC analog signal may be upconverted to a radar frequency and transmitted. A receiver may receive, downconvert, and analyze a reflection of the radar transmission, e.g., to perform range detection based on a frequency ramp encoded by the radar transmission.

Techniques for compensating high-speed digital-to-analog converters (DACs) for static mismatch are described. In ideal circumstances, the current sources of a DAC are identical to each other, leading to a frequency response presenting a relatively flat noise spectrum. In the presence of mismatch, however, the response creates unwanted spurious content, which can negatively affect the DAC's dynamic range. The techniques described herein involve randomized thermometric encoders. First, the direction in which a packet contracts or expands, depending on the value to be encoded, can be randomized. Second, pairs of values in a packet (and/or pairs of values outside the packet) can be swapped with one another in a randomized fashion. Third, the decision of whether to apply randomization or not can itself be randomized. By applying one or more of the randomization techniques described herein, the negative effects of switch timing offset and errors in DC linearity can be mitigated.

A time-interleaved analog to digital converter includes first and second capacitor array circuits, first and second transfer circuits, a fine converter circuitry, and an encoder circuit. The capacitor array circuits sample an input signal and generate first residues according to first quantization signals. The first and second transfer circuits transfer first and second residues respectively. The fine converter circuitry performs a noise shaping signal conversion on the first and second residues to generate a second quantization signal. A turn-on time of the corresponding first transfer circuit is determined based on the coarse conversion corresponding to a first capacitor array circuit and the noise shaping signal conversion corresponding to a second capacitor array circuit to selectively bring forward a start time of the noise shaping signal conversion. The encoder circuit generates a digital output according to the first and the second quantization signals.

A system and method of digital to analog conversion including modulating a digital value D.sub.N-K with an oversampling delta sigma modulator to provide an M-bit coarse quantized value DM, in which D.sub.N-K comprises N-K least significant bits of an N-bit digital input value D.sub.N and in which quantization error may be shaped to a higher frequency above a signal band of interest, adding D.sub.M to a value D.sub.K to provide a select value D.sub.KM in which D.sub.K includes the K remaining most significant bits of D.sub.N, and applying mismatch shaping of a total of at least P=2.sup.K elements of a P-element DAC per cycle based on D.sub.KM to provide an analog output value. The analog output value may be filtered with a low-pass filter to provide a filtered analog output value. An order of low-pass filtering may be one more than an order of modulating.

Described herein is a mismatch shaping technique applied in digital-to-analog converters (DACs) for high pass filtering mismatch related errors. The mismatch shaping scheme is based on a zero mean error encoding technique, which can be applied directly to binary coded signals, without the use for binary to thermometer decoding and element shuffling. In at least one example, an apparatus is provided which comprises a mismatch shaping circuitry to receive an N-bit binary input bits and to generate an (N+1)-bit digital output. In at least one example, the apparatus further comprises a digital-to-analog converter to receive the (N+1)-bit digital output and to generate an analog output, wherein the mismatch shaping circuitry is to encode the (N+1)-bit digital output to shape mismatch errors in the digital-to-analog converter.

A digital noise coupling circuit includes: an analog-to-digital converter (ADC) configured to convert a quantization error, generated in a process of converting a first analog signal into a first digital signal, into a first digital error signal; a delay cell comprising delay elements configured to delay a transmission of the first digital error signal based on a clock signal; and a digital-to-analog (DA) conversion circuit configured to perform, in an analog domain, noise shaping on the first digital error signal that is delayed and transmitted from the delay cell.

A low-pass and band-pass delta-sigma () analog-to-digital converter (ADC) device for sensor interface is disclosed. The device includes a first stage comprising a low-resolution passive integrator-based noise-shaping successive approximation register (SAR) ADC and a second stage comprising a voltage-controlled oscillator (VCO)-ADC.