A digital-to-analog conversion circuit is used for converting a first digital input into a first analog output, and includes a segmentation circuit, a plurality of multi-bit dynamic element matching digital-to-analog converters (DEM DACs), and a combination circuit. The segmentation circuit applies segmentation to the first digital input to generate a plurality of code segments. The multi-bit DEM DACs convert the code segments into a plurality of DAC outputs, respectively, wherein the multi-bit DEM DACs include at least a first multi-bit DEM DAC and a second multi-bit DEM DAC, and the first multi-bit DEM DAC and the second multi-bit DEM DAC employ different DEM techniques. The combination circuit combines the DAC outputs to generate the first analog output.

A device includes a local oscillator, an all-digital phase-locked loop, a digital signal generator, sampling circuitry, and an interface. The local oscillator generates a local clock signal. The all-digital phase locked loop generates a sampling control signal. The ADPLL includes a phase-error detector, a digital filter and a sigma-delta modulator. The phase detector generates a phase error signal based on a loop clock signal and a received reference signal. The digital filter generates a signal indicative of a frequency ratio between a frequency of the reference clock signal and the local clock frequency based on the phase error signal. The sigma-delta modulator generates a modulated signal based on the signal indicative of the frequency ratio. The sampling control signal is based on the modulated signal. The sampling circuitry samples digital signals generated by the digital signal generator at a sampling frequency, which is a function of the sampling control signal.

A quantizer includes: a quantizer capacitor having a first end and a second end; an input calculator that receives input voltages, sums the input voltages, and outputs the summed result to the first end of the quantizer capacitor; a scaler that receives reference voltages and a scale code, generates a scale voltage from the reference voltages depending on the scale code, and outputs the scale voltage to the second end of the quantizer capacitor; and a latch that stores an output voltage of the first end of the quantizer capacitor.

In accordance with embodiments of the present disclosure, a digital microphone system may include a microphone transducer and a digital processing system. The microphone transducer may be configured to generate an analog input signal indicative of audio sounds incident upon the microphone transducer. The digital processing system may be configured to convert the analog input signal into a first digital signal having a plurality (e.g., more than 3) of quantization levels, and in the digital domain, process the first digital signal to compress the first digital signal into a second digital signal having fewer quantization levels (e.g., +1, 0, 1) than that of the first digital signal.

Provided, among other things, is an apparatus that converts a signal from one sampling domain to another, and which includes: an input line for accepting an input signal and a processing branch. The processing branch includes a branch input coupled to the input line for inputting data samples that are discrete in time and in value, a quadrature downconverter, a first and second lowpass filter, a first and second polynomial interpolator, and a rotation matrix multiplier that provides a phase rotation. The processing branch generates data samples at a sampling interval that differs from the sampling interval associated with the signal provided to the branch input, e.g., with the difference in the sampling intervals depending on fluctuations in the output period of a local oscillator. Certain embodiments include multiple such processing branches, e.g., operating on different frequency bands of the input signal.

Methods and apparatus for shaping and filtering quantization errors conjointly in space and time to produce a higher-precision output in a spatially and temporally oversampled array. A space-time error-shaping array system has an array of sensors, each sensor producing a temporal signal comprising quantized waveforms. A multi-input multiple-output (MIMO) discrete-time filter structure with multiple inputs, each coupled to a sensor of the array of sensors, shapes quantization errors of the array of sensors on the basis of temporal aspects of the quantized waveforms conjointly with spatial aspects of the quantized waveforms.

A quantizer includes: a quantizer capacitor having a first end and a second end; an input calculator that receives input voltages, sums the input voltages, and outputs the summed result to the first end of the quantizer capacitor; a scaler that receives reference voltages and a scale code, generates a scale voltage from the reference voltages depending on the scale code, and outputs the scale voltage to the second end of the quantizer capacitor; and a latch that stores an output voltage of the first end of the quantizer capacitor.

The disclosure relates to a microphone assembly including a multibit analog-to-digital converter configured to generate N-bit samples representative of a microphone signal. The microphone assembly also includes a first digital-to-digital converter configured to generate a corresponding M-bit digital signal based on N-bit digital samples, wherein N and M are positive integers and N>M. The microphone assembly may include a data interface configured to repeatedly receive samples of the M-bit digital signal and write bits of the M-bit digital signal to a data frame.

The present disclosure provides a converting module formed in a first die. The first die is coupled to a bus having a bus bit width. The converting module includes an analog-to-digital converter, configured to generate a first digital signal having a first bit width different from the bus bit width; and a sigma-delta modulator, coupled to the analog-to-digital converter, and configured to generate a second digital signal according to the first digital signal. The second digital signal has a bit width equal to the bus bit width. The sigma-delta modulator includes a filter and a quantizer. The number of bits outputted by the quantizer is equal to the bus bit width.

Systems and methods according to one or more embodiments are provided for improving noise performance in a delta sigma modulator comprising an adder, quantizer and nth order filter. The adder is operable to receive an input signal and a feedback signal, and output a modified input signal. The quantizer is operable to receive the modified input signal and output a quantized output signal, the quantized output signal having a corresponding quantization error. The nth order filter is operable to receive a quantization error value and generate the feedback signal, the nth order filter comprising a first memory element having a first error value, a second memory element having a second error value, and a gravity component operable to converge the first error value and the second error value when the input signal is approximately zero.