Described herein are systems and methods that provide for asymmetric image splitter image stream applications. In one embodiment, a system supporting image multi-streaming comprises an asymmetric image splitter engine that splits super-frame image streams into two or more image streams and a fractional clock divider circuit. The fractional clock divider may comprise a digital feedback control loop and a one-bit sigma delta modulator. The fractional clock divider circuit may provide compatible display clock frequencies for each of the two or more image streams. When a multi-image stream comprises the two image streams, the asymmetric image splitter engine adjusts a vertical asymmetry of a first image stream with a shortest height to same height as a second image stream by adding vertical padding to the first image stream. The super-frame image streams may comprise image streams from video, LIDAR, radar, or other sensors.

A second-order modulator includes a plurality of integrators and a parallel higher-bit processing part, and the parallel higher-bit processing part includes a plurality of addition and determination processing sections. The addition and determination processing section receives first and second carry inputs and first and second state inputs, and outputs a quantized output and first and second state outputs. A first selector selects one set from sets of the first and the second state outputs from the plurality of addition and determination processing sections and outputs the selected set, and a second selector selects one quantized output from the quantized outputs from the plurality of addition and determination processing sections. An output of the first selector is used as a selection control signal for the first and the second selectors.

A problem with conventional distortion pulse shift circuits is that the output timing of a pulse signal cannot be controlled unless a reset signal is used. A pulse shift circuit according to the present invention includes: an integrator to integrate, for every clock, the first signal to be inputted; a quantizer to receive the second signal and to output a pulse signal when an integrated value of the integrator becomes equal to or larger than a signal value of the second signal; a delay circuit to delay the pulse signal; a converter disposed before or after the delay circuit to convert a signal value of the pulse signal into the signal value of the second signal; a subtractor to subtract the signal value of the pulse signal converted by the converter, from the signal value of the first signal to be inputted to the integrator; and an input signal control circuit to receive a third signal, to be disposed before the integrator, and to add a signal value corresponding to the third signal to the first signal to be inputted to the integrator or to block the first signal from being inputted to the integrator for clocks corresponding to the third signal.

In accordance with embodiments of the present disclosure, a digital microphone system may include a microphone transducer and a digital processing system. The microphone transducer may be configured to generate an analog input signal indicative of audio sounds incident upon the microphone transducer. The digital processing system may be configured to convert the analog input signal into a first digital signal having a plurality (e.g., more than 3) of quantization levels, and in the digital domain, process the first digital signal to compress the first digital signal into a second digital signal having fewer quantization levels (e.g., +1, 0, 1) than that of the first digital signal.

The present disclosure relates to a compression/encoding apparatus and method, a decoding apparatus and method, and a program that allow for provision of a lossless compression technology with higher compression ratio.

A GOB data configuration section configures GOB data with a group of digital data that includes a plurality of blocks by treating a frame of delta-sigma-modulated digital data as a block. A table generation section generates a conversion table for encoding the GOB data. An encoding section compresses and encodes the digital data of each block included in the GOB data by using the conversion table. The present technology is applicable, for example, to audio signal compression and encoding, and so on.

A problem with conventional distortion pulse shift circuits is that the output timing of a pulse signal cannot be controlled unless a reset signal is used. A pulse shift circuit according to the present invention includes: an integrator to integrate, for every clock, the first signal to be inputted; a quantizer to receive the second signal and to output a pulse signal when an integrated value of the integrator becomes equal to or larger than a signal value of the second signal; a delay circuit to delay the pulse signal; a converter disposed before or after the delay circuit to convert a signal value of the pulse signal into the signal value of the second signal; a subtractor to subtract the signal value of the pulse signal converted by the converter, from the signal value of the first signal to be inputted to the integrator; and an input signal control circuit to receive a third signal, to be disposed before the integrator, and to add a signal value corresponding to the third signal to the first signal to be inputted to the integrator or to block the first signal from being inputted to the integrator for clocks corresponding to the third signal.

To correct for non-linearities in the response of a microphone as a function of sound pressure level incident upon the microphone, a displacement non-linearity function is applied to the signal path of the microphone, wherein the displacement non-linearity function is a function of the digital audio output signal and has a response modeling non-linearities of the displacement as a function of a sound pressure level incident upon the microphone.

A system and method of digital to analog conversion including modulating a digital value D.sub.N-K with an oversampling delta sigma modulator to provide an M-bit coarse quantized value DM, in which D.sub.N-K comprises N-K least significant bits of an N-bit digital input value D.sub.N and in which quantization error may be shaped to a higher frequency above a signal band of interest, adding D.sub.M to a value D.sub.K to provide a select value D.sub.KM in which D.sub.K includes the K remaining most significant bits of D.sub.N, and applying mismatch shaping of a total of at least P=2.sup.K elements of a P-element DAC per cycle based on D.sub.KM to provide an analog output value. The analog output value may be filtered with a low-pass filter to provide a filtered analog output value. An order of low-pass filtering may be one more than an order of modulating.

A system for determining one or more coefficients of a filter is presented. The system includes a modulated ramp generator including a ramp generator, a delta-sigma modulator coupled to the ramp generator and configured to generate a control signal, and a control output coupled to the delta-sigma modulator and configured to receive the control signal; and a filter coupled to the control output and configured to receive the control signal from the control output, the filter including one or more configurable coefficients, values of the configurable coefficients being selected by the control signal, an input for receiving a filterable signal, and an output for providing a filtered signal.