A coherent optical modem includes an optical interface; and circuitry connected to the optical interface and configured to detect a first timing reference point in a transmit Digital Signal Processor (DSP) frame in a transmit direction from a first node to a second node, and detect a second timing reference point in a receive DSP frame in a receive direction from the second node to the first node, wherein the first timing reference point and the second timing reference point are determined based on a pattern in any DSP frame field including i) padding area, ii) a reserved area, and iii) a DSP Multi-Frame Alignment Signal (MFAS) area. The pattern can be input in select DSP frames for a time period that is greater than a time period for each DSP frame.

Systems and methods for clock synchronization are disclosed in which a primary node generates special physical layer clock sync symbols from the output of a reference clock and inserts the clock sync symbols within a symbol stream to one or more secondary nodes. Upon receiving a symbol stream, a secondary node can extract the clock sync symbols from the stream to synchronize its local clock with the reference clock of the primary node. In particular, the clock sync symbols can be inserted into the symbol stream at any arbitrary symbol location, e.g., even between consecutive symbols of a symbol encoded data frame. The clock sync symbols can also replace some control symbols in the symbol stream, such as idle or comma symbols. Accordingly, the clock sync symbols can be inserted into a symbol stream at fixed intervals, irregular intervals, or at any arbitrary time for high resolution clock synchronization.

A subscriber of a wired data network, in particular of a local bus system, having internal clock generator for generating a clock generator signal having a clock generator frequency for the subscriber, a receive circuit for receiving a serial receive data stream, a processing circuit for inputting parallel receive data and for outputting parallel transmit data, and a transmit circuit for transmitting a serial transmit data stream. The receive circuit has a serial-to-parallel converter for converting serial receive data of the serial receive data stream into the parallel receive data. The receive circuit has a synchronization unit for synchronizing the internal clock generator to the data clock frequency contained in the serial receive data stream. The synchronization unit is configured for detecting transitions in the received serial receive data stream and for controlling the clock generator frequency of the internal clock generator as a function of the detected transitions.

A method for processing a packet in a mobile communication network and a network element for performing the same. A first network element may receive a first data packet to be transmitted to a second network element via a third network element and add a header to the first data packet. The first network element may add time information associated with the first data packet to the header and transmit the first data packet with the header to the third network element.

Techniques for clock manager monitoring for time sensitive networks are described. An apparatus, comprises a clock circuitry to manage a clock for a device, a processing circuitry coupled to the clock circuitry, the processing circuitry to execute instructions to perform operations for a clock manager, the clock manager to receive messages with time information for a network and generate clock manager control information to adjust the clock to a network time for the network, and a detector coupled to the processing circuitry and the clock circuitry, the detector to receive the clock manager control information, generate model control information based on a clock model, compare the clock manager control information with the model control information to generate difference information, and determine whether to generate an alert based on the difference information. Other embodiments are described and claimed.

The disclosure provides satellite communication methods and related devices. One example method includes that a device receives a first common timing advance (TA) parameter and a first common TA change amount calculation parameter, where the first common TA parameter is used to obtain a first common TA, and the first common TA change amount calculation parameter is used to update the first common TA to obtain an updated common TA. The device sends a random access preamble by using the updated common TA.

To improve integrity of time synchronization, a node in the safety rated system takes steps to ensure the time to which it is synchronized has not become corrupted. The node receives a synchronize request message from an adjacent network device, which includes the master time, and the node generates an offset value corresponding to a difference between a local time and the master time. The node stores the offset time into a safety memory to ensure that the offset value has data integrity and does not become corrupted. The node performs periodic skew detection between two devices to verify that the clocks remain synchronized. In addition, the node performs a local drift detection to detect if the frequency of the local oscillator on which the local clock value is based begins to change.

The communication system is provided, where the communication system comprises multiple cluster distributed antenna system (MC-DAS) network and a controller. Each cluster in the MC-DAS comprises a cluster master (CM) and remote radio units (RRU), which are in the coverage area of the controller. The controller and the DAS clusters are synchronized using a hierarchical precision time protocol (HPTP). Each DAS cluster is configured to transmit messages independently from other DAS clusters in the plurality of DAS clusters using a distributed cyclic delay diversity (CDD) scheme with a determined length of a cyclic prefix. The controller further comprises a controller configured to transmit a message from the controller to a receiver through one or more DAS clusters of the plurality of the DAS clusters.

Systems and methods for clock synchronization are disclosed in which a primary node generates special physical layer clock sync symbols from the output of a reference clock and inserts the clock sync symbols within a symbol stream to one or more secondary nodes. Upon receiving a symbol stream, a secondary node can extract the clock sync symbols from the stream to synchronize its local clock with the reference clock of the primary node. In particular, the clock sync symbols can be inserted into the symbol stream at any arbitrary symbol location, e.g., even between consecutive symbols of a symbol encoded data frame. The clock sync symbols can also replace some control symbols in the symbol stream, such as idle or comma symbols. Accordingly, the clock sync symbols can be inserted into a symbol stream at fixed intervals, irregular intervals, or at any arbitrary time for high resolution clock synchronization.

The precision time protocol (PTP) runs on the peer switches in an MLAG domain. PTP messages received by one peer switch on an MLAG interface is selectively peer-forwarded to the other peer switch on the same MLAG interface in order to coordinate a synchronization session with a PTP node. The peer-forwarded messages inform one peer switch to be an active peer and the other peer switch to be an inactive peer so that timestamped messages during the synchronization session are exchanged only between the PTP node the active peer, and hence take the same data path.