H04L25/03044

RECEIVING DEVICE
20190020508 · 2019-01-17 · ·

A receiving device includes: a resampler to convert a sampling rate of a reception signal, and output a first signal that is a signal having been subjected to sampling rate conversion; an equalizer to perform an adaptive equalization process using the first signal as an input, and output a second signal that is a signal having been subjected to the adaptive equalization process and having a sampling rate that is an integer fraction of an input signal; a correlation calculator to calculate a correlation function between the first signal and the second signal; and a rate controller to control a rate conversion ratio for sampling rate conversion in the resampler on a basis of the correlation function.

FINITE IMPULSE RESPONSE ANALOG RECEIVE FILTER WITH AMPLIFIER-BASED DELAY CHAIN

High-data rate channel interface modules and equalization methods employing a finite impulse response (FIR) analog receive filter. Embodiments include an illustrative channel interface module having multiple amplifier-based delay units arranged in a sequential chain to convert an analog input signal into a set of increasingly-delayed analog signals that are weighted and combined together with the analog input signal to form an equalized signal; and a symbol decision element operating on the equalized signal to obtain a sequence of symbol decisions. An interface that extracts received data from the sequence of symbol decisions. The delay units may employ one or more delay cells each having a common-source amplifier stage followed by a source follower output stage, the two stages providing approximately equal portions of the propagation delay. An enhanced gate-to-drain capacitance in the common-source amplifier may increase propagation delay while reducing bandwidth limitations.

Adjustment method and device for equalizer coefficient, and computer storage medium
20180152328 · 2018-05-31 ·

A jones matrix is obtained using coefficients of an equalizer; a parameter of the jones matrix is obtained; a coefficient of an X axis polarization state or a Y axis polarization state in the coefficients is adjusted using the parameter of the jones matrix when the coefficients have singularity characteristics, or energy corresponding to each coefficient of X or Y axis polarization state under each order of a filter in the equalizer is determined using two coefficients of an X or Y axis polarization state in the equalizer coefficients; and a central position of a coefficient tap of X or Y axis polarization state of the equalizer is adjusted using the energy corresponding to each coefficient of X or Y axis polarization state under each order of the filter when the coefficient tap of the X axis or Y axis polarization state of the equalizer deviates from the central position.

SLICED ARCHITECTURE FOR A CURRENT MODE DRIVER
20180062978 · 2018-03-01 · ·

A method may include hardwiring: a first dynamic input of M slices in a section of a sliced architecture to receive a main data sample; and a second dynamic input of each of X and Y slices to respectively receive a first or second delayed data sample, X, Y being subsets of M. A slice current may be multiplied with: the data sample in each of A of the M slices; and the first delayed data sample in each of B of the X slices. The method may also include summing: outputs of the A slices to obtain a weighted output current of the data sample; outputs of the B slices to obtain a weighted output current of the first delayed data sample; and the weighted output currents of the main data sample and of the first delayed data sample to obtain a net weighted output current of the section.

DELAY-BASED NONLINEAR EQUALIZER
20170187463 · 2017-06-29 ·

A method and system for implementing nonlinear transmitter equalization may employ a feed-forward equalizer that applies transition-dependent delays at each tap. Each delay element in a delay line may include independent controls for the delays to be applied to rising transitions and for the delays to be applied to falling transitions. Different delays may be applied to transitions between any two levels in a signal that is encoded using three or more analog levels. Different amounts of weighting may be applied to the output of each delay element in the delay line by respective tap weighing elements. A combiner circuit may generate an output for the equalizer as a linear combination of the weighted outputs of the delay elements. The output of the equalizer may be an input to a vertical cavity surface emitting laser (VCSEL) and may compensate for a nonlinearity of the VCSEL.

Blind equalization tap coefficient adaptation in optical systems

A method of blind tap coefficient adaptation includes receiving a digital data signal including random digital data, equalizing a first portion of the digital data signal using a first set of predetermined tap coefficients and a second portion of the digital data signal using a second set of predetermined tap coefficients. The method includes generating a first eye diagram and a second eye diagram from a first portion and a second portion of an equalized signal, respectively. The first eye diagram is compared with the second eye diagram to determine which of the sets of predetermined tap coefficients results in a data signal having a higher signal quality. The method includes inputting to an equalizer as an initial set of tap coefficients the first set of predetermined tap coefficients or the second set of predetermined tap coefficients according to the determination.

Symbol timing estimation for coherent polarization multiplex optical receivers

A received POLMUX signal is rotated by fixed rotation parameters (Rot0, Rot1, Rot2) and the rotated POLMUX signal with optimal signal performance is selected and phase information is derived from both polarities. A pre-filter improves the timing accuracy.

Scalable receiver architecture for silicon photonic links
12418347 · 2025-09-16 · ·

Sampling circuitry for receiving an analog signal from photodetector circuitry and generating a sample analog signal. Equalization circuitry for generating an equalized signal comprising first and second sample values corresponding with a cursor tap and a first postcursor tap, and one or more third sample values corresponding with taps other than the cursor tap and the first postcursor tap. In the equalized signal, amplitudes of the first and second sample values are substantially equal while the third sample values are attenuated relative to the first and second sample values. The first and second sample values correspond with two or more first symbols of a first alphabet. Data slicer and modulo circuitry to generate a data signal based on the equalized signal and perform a modulo operation on the two or more first symbols and to generate one or more second symbols. The second symbols are according to a second alphabet.