Digital pre-distortion is performed on a received signal using a set of pre-distortion coefficients to produce a digital pre-distorted signal. The digital pre-distorted signal is converted to an analog signal, which is amplified to produce a transmission output signal. The transmission output signal is converted to a digital feedback signal. A plurality of fractional delay filters is applied to the digital feedback signal to obtain a plurality of fractional delay compensated (FDC) candidates, and gain compensation is applied to each of the plurality of FDC candidates to obtain a plurality of gain and fractional delay compensated (XFT) candidates. The digital pre-distorted signal is used as a reference signal, and the XFT candidates and the reference signal are used to select a selected XFT candidate of the plurality of XFT candidates. The selected XFT candidate is used to generate the set of pre-distortion coefficients.

A multi-phase partial response receiver supports various incoming data rates by sampling PrDFE output values at a selected one of at least two clock phases. The receiver includes a calibration circuit that performs a timing analysis of critical data paths in the circuit, and this analysis is then used to select the particular clock phase used to latch the output values. These techniques permit the multiplexer outputs from for each phase of the partial response receiver to directly drive selection of a multiplexer for the ensuing phase, i.e., by avoiding regions of instability or uncertainty in the respective multiplexer outputs.

A multi-phase partial response receiver supports various incoming data rates by sampling PrDFE output values at a selected one of at least two clock phases. The receiver includes a calibration circuit that performs a timing analysis of critical data paths in the circuit, and this analysis is then used to select the particular clock phase used to latch the output values. These techniques permit the multiplexer outputs from for each phase of the partial response receiver to directly drive selection of a multiplexer for the ensuing phase, i.e., by avoiding regions of instability or uncertainty in the respective multiplexer outputs.

A multi-phase partial response receiver supports various incoming data rates by sampling PrDFE output values at a selected one of at least two clock phases. The receiver includes a calibration circuit that performs a timing analysis of critical data paths in the circuit, and this analysis is then used to select the particular clock phase used to latch the output values. These techniques permit the multiplexer outputs from for each phase of the partial response receiver to directly drive selection of a multiplexer for the ensuing phase, i.e., by avoiding regions of instability or uncertainty in the respective multiplexer outputs.

An apparatus for performing fractionally spaced adaptive equalization with non-integer sub-symbol sampling has an adaptive equalizer that receives a continuous stream of input data having a non-integer, fractional delay between consecutive samples at a non-integer, sub-symbol rate and outputs a stream of equalized data based on tap weights of taps of the adaptive equalizer that are spaced at an interval corresponding to the non-integer, sub-symbol rate. The tap weights are updated independently of the fractional delay between consecutive samples of the input data using an error signal. An equalizer output alignment component downstream of the adaptive equalizer aligns the stream of equalized data with a corresponding transmitted symbol.

An adaptive equalizer includes: a speculative equalization circuit which operates a plurality of first tap coefficients with respect to input data and selects operation data corresponding to the input data from a plurality of operation data obtained by the operation; and an adaptive equalization circuit which generates the plurality of first tap coefficients, on the basis of the input data. The adaptive equalization circuit includes: an operation circuit which selects one of a plurality of second tap coefficients corresponding to the plurality of first tap coefficients and operates the selected second tap coefficient with respect to the input data; and a tap coefficient generation circuit which generates the plurality of first tap coefficients, on the basis of operation data obtained by the operation of the operation circuit, when the second tap coefficient selected at the time of the operation in the operation circuit corresponds to the first tap coefficient used for the operation of the operation data selected in the speculative equalization circuit.

An adaptive equalizer includes: a speculative equalization circuit which operates a plurality of first tap coefficients with respect to input data and selects operation data corresponding to the input data from a plurality of operation data obtained by the operation; and an adaptive equalization circuit which generates the plurality of first tap coefficients, on the basis of the input data. The adaptive equalization circuit includes: an operation circuit which selects one of a plurality of second tap coefficients corresponding to the plurality of first tap coefficients and operates the selected second tap coefficient with respect to the input data; and a tap coefficient generation circuit which generates the plurality of first tap coefficients, on the basis of operation data obtained by the operation of the operation circuit, when the second tap coefficient selected at the time of the operation in the operation circuit corresponds to the first tap coefficient used for the operation of the operation data selected in the speculative equalization circuit.

A multi-phase partial response receiver supports various incoming data rates by sampling PrDFE output values at a selected one of at least two clock phases. The receiver includes a calibration circuit that performs a timing analysis of critical data paths in the circuit, and this analysis is then used to select the particular clock phase used to latch the output values. These techniques permit the multiplexer outputs from for each phase of the partial response receiver to directly drive selection of a multiplexer for the ensuing phase, i.e., by avoiding regions of instability or uncertainty in the respective multiplexer outputs.

A decision-feedback equalizer for use in a receiver unit for receiving an incoming data stream and for providing a stream of bit data outputs includes a plurality of asynchronous comparators and a fastest decision detector unit operatively coupled with the asynchronous comparators. Each of the asynchronous comparators is configured to receive an input signal and to directly provide a comparison result output in an asynchronous manner. The fastest decision detector unit is configured for receiving at least a subset of the respective comparison result outputs of the asynchronous comparators and for forwarding the comparison result of one of the asynchronous comparators towards the output of the decision-feedback equalizer. The fastest decision detector unit is configured to select a given one of the asynchronous comparators as one which firstly provided its comparison result output.

A decision-feedback equalizer for use in a receiver unit for receiving an incoming data stream and for providing a stream of bit data outputs includes a plurality of asynchronous comparators and a fastest decision detector unit operatively coupled with the asynchronous comparators. Each of the asynchronous comparators is configured to receive an input signal and to directly provide a comparison result output in an asynchronous manner. The fastest decision detector unit is configured for receiving at least a subset of the respective comparison result outputs of the asynchronous comparators and for forwarding the comparison result of one of the asynchronous comparators towards the output of the decision-feedback equalizer. The fastest decision detector unit is configured to select a given one of the asynchronous comparators as one which firstly provided its comparison result output.