A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

An integrated circuit (IC) memory controller includes receiver circuitry to receive read data from a memory. The receiver circuitry includes equalization circuitry having at least one tap to apply data level equalization to the read data, and a tap weight adapter circuit. The tap weight adapter circuit adaptively generates a data level tap weight corresponding to the data level equalization from an edge analysis of previously received read data.

A technique for wireless signal processing performed at a receiver in a wireless network includes receiving, by a wireless receiver, an orthogonal frequency division multiplexing (OFDM) signal on a shared downlink channel from the wireless network, wherein the OFDM signal includes contribution from a serving cell signal and at least one interfering signal, obtaining an estimate of the serving cell signal, calculating a residual signal by subtracting the estimate of the serving cell signal from the OFDM signal, generating a whitened residual signal by whitening the residual signal, obtaining an estimate of a modulation scheme of the at least one interfering signal by performing a likelihood-based blind classification on the whitened residual signal, and performing further receiver-side processing of the serving cell signal using the estimate of the modulation scheme of the at least one interfering signal.

A receiver includes a continuous-time equalizer, a decision-feedback equalizer (DFE), data and error sampling logic, and an adaptation engine. The receiver corrects for inter-symbol interference (ISI) associated with the most recent data symbol (first post cursor ISI) by establishing appropriate equalization settings for the continuous-time equalizer based upon a measure of the first-post-cursor ISI.

System and method of timing recovery for recovering a clock signal with reduced interference with clock phase correction by an adaptive equalizer. The equalizer in the timing recovery loop is dynamically adapted to the current channel characteristics that vary over time. The equalizer includes compensation logic operable to detect and compensate a correction of clock phase ascribed to the equalization adaptation. The compensation logic can calculate the offset between a center of filter (COF) value and a COF nominal value, the offset indicative of the amount and direction of clock phase correction contributed by the equalizer. Based on the offset, the compensation logic adjusts the equalized signal by adjusting the tap weights of the equalizer to correct the offset, thereby compensating the clock phase correction.

The object of the present invention is to reduce the number of complex multiplications in an ICI reduction processing and to reduce the influence of characteristic degradation due to a quantization bit limitation of a digital signal processing. A receiver includes an extended CP addition unit (102) that receives radio signals through a plurality of paths and compensates for a symbol lost within a Fourier transform window to received signals received through the plurality of paths; and FFTs (104-1 and 104-2) each of which performs, in a range of the Fourier transform window, Fourier transform on the received signal with a lost symbol added.

A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

A receiver includes a continuous-time equalizer, a decision-feedback equalizer (DFE), data and error sampling logic, and an adaptation engine. The receiver corrects for inter-symbol interference (ISI) associated with the most recent data symbol (first post cursor ISI) by establishing appropriate equalization settings for the continuous-time equalizer based upon a measure of the first-post-cursor ISI.

The object of the present invention is to reduce the number of complex multiplications in an ICI reduction processing and to reduce the influence of characteristic degradation due to a quantization bit limitation of a digital signal processing. A receiver includes an extended CP addition unit (102) that receives radio signals through a plurality of paths and compensates for a symbol lost within a Fourier transform window to received signals received through the plurality of paths; and FFTs (104-1 and 104-2) each of which performs, in a range of the Fourier transform window, Fourier transform on the received signal with a lost symbol added.

A method of blind tap coefficient adaptation includes receiving a digital data signal including random digital data, equalizing a first portion of the digital data signal using a first set of predetermined tap coefficients and a second portion of the digital data signal using a second set of predetermined tap coefficients. The method includes generating a first eye diagram and a second eye diagram from a first portion and a second portion of an equalized signal, respectively. The first eye diagram is compared with the second eye diagram to determine which of the sets of predetermined tap coefficients results in a data signal having a higher signal quality. The method includes inputting to an equalizer as an initial set of tap coefficients the first set of predetermined tap coefficients or the second set of predetermined tap coefficients according to the determination.