Equalization circuitry for a data channel in an integrated circuit device includes an analog equalization stage coupled to the data channel, and a digital signal processing stage downstream of the analog equalization stage. The digital signal processing stage generates control signals to control the analog equalization stage, and includes a digital equalization stage that operates on output of the analog equalization stage. The analog equalization stage may further include an enhanced processing stage for optical signals, which may be selectably coupled to the analog equalization stage. The analog equalization stage may include at least one feed-forward or feedback equalization stage, and a decision stage that outputs decision signals at one of a first plurality of signal levels. The enhanced processing stage operates on the decision signals to output enhanced decision signals at one of a second plurality of signal levels of higher resolution than the first plurality of signal levels.

Decision feedback equalization (DFE) is used to help reduce inter-symbol interference (ISI) from a data signal received via a band-limited (or otherwise non-ideal) channel. A first PAM-4 DFE architecture has low latency from the output of the samplers to the application of the first DFE tap feedback to the input signal. This is accomplished by not decoding the sampler outputs in order to generate the feedback signal for the first DFE tap. Rather, weighted versions of the raw sampler outputs are applied directly to the input signal without further analog or digital processing. Additional PAM-4 DFE architectures use the current symbol in addition to previous symbol(s) to determine the DFE feedback signal. Another architecture transmits PAM-4 signaling using non-uniform pre-emphasis. The non-uniform pre-emphasis allows a speculative DFE receiver to resolve the transmitted PAM-4 signals with fewer comparators/samplers.

Methods and systems are described for sampling a data signal using a data sampler operating in a data signal processing path having a decision threshold associated with a decision feedback equalization (DFE) correction factor, measuring an eye opening of the data signal by adjusting a decision threshold of a spare sampler operating outside of the data signal processing path to determine a center-of-eye value for the decision threshold of the spare sampler, initializing the decision threshold of the spare sampler based on the center-of-eye value and the DFE correction factor, generating respective sets of phase-error signals for the spare sampler and the data sampler responsive to a detection of a predetermined data pattern, and updating the decision threshold of the data sampler based on an accumulation of differences in phase-error signals of the respective sets of phase-error signals.

Decision feedback equalization (DFE) is used to help reduce inter-symbol interference (ISI) from a data signal received via a band-limited (or otherwise non-ideal) channel. A first PAM-4 DFE architecture has low latency from the output of the samplers to the application of the first DFE tap feedback to the input signal. This is accomplished by not decoding the sampler outputs in order to generate the feedback signal for the first DFE tap. Rather, weighted versions of the raw sampler outputs are applied directly to the input signal without further analog or digital processing. Additional PAM-4 DFE architectures use the current symbol in addition to previous symbol(s) to determine the DFE feedback signal. Another architecture transmits PAM-4 signaling using non-uniform pre-emphasis. The non-uniform pre-emphasis allows a speculative DFE receiver to resolve the transmitted PAM-4 signals with fewer comparators/samplers.

Disclosed is a power-optimized distributed arithmetic (DA)-based feed forward equalizer (FFE) that performs on-demand equalization processing of a data sample. Specifically, a data stream is represented by digital words, which indicate signal levels at taps on a transmission medium. A screener applies formulas to selected taps as opposed to all taps (e.g., to the main cursor tap, which corresponds to the current data sample, and to specific pre-cursor and post-cursor taps, which correspond to immediately proceeding and following data samples) to determine whether the current data sample (which should indicate a specific two-bit symbol) has degraded during transmission to a point where equalization processing is required. If so, a bypass flag is set to a first level so that the data sample is subjected to equalization processing. If not, the bypass flag is set to a second level so that such processing is bypassed. Also disclosed is a corresponding method.

A method for adapting a continuous time equalizer (CTE) includes determining a gain of a discrete time equalizer (DTE) and determining whether the gain has increased or decreased by more than the threshold amount. Responsive to determining that the gain has increased or decreased by more than the threshold amount, the method includes sequentially configuring the CTE for multiple CTE settings such that gain of the CTE is caused to increase or decrease in a same direction with the change in gain of the DTE. The method also includes determining a separate figure of merit (FOM) for each of the multiple CTE settings and selecting a new CTE setting from the multiple CTE settings based on the FOM for each of the multiple CTE settings.

A comparator includes a resolver controlled by a resolver clock signal and a differential amplifier controlled by a sampling clock signal. The resolver clock signal and the sampling clock signal are such that amplification at the differential amplifier during the reset phase of the resolver clock signal and the reset phase of the sampling clock signal begins during the resolving phase of the resolver.

A circuit and method for reducing intersymbol interference due to pre-cursor distortion. A first set of circuit elements located along a first circuit path of a receiver device process an analog input signal of the receiver to form an equalized representation of the input signal. A second set of circuit elements are located along a second circuit path that has lower latency than the first circuit path. The second set of circuit elements form a scaled signal as one of the following: a scaled representation of the input signal, an inverted scaled representation of the input signal, a scaled derivative of the input signal, and an inverted scaled derivative of the input signal. The scaled signal is combined with the equalized representation to cancel out a pre-cursor portion of the equalized representation.

Apparatus and methods may provide improved equalizer performance, e.g., for optical-fiber-based communication systems. A least-mean-square (LMS) equalizer may include a decision feedback path containing feedback carrier recovery (FBCR), which may have low latency, and which may thus enable high-speed tap updating in the equalizer. Feed-forward carrier recovery (FFCR) may be applied, in parallel with the FBCR, to provide equalizer output by compensating, e.g., for phase noise, with improved carrier recovery/compensation, versus using FBCR to generate the output.

An improved receiver design implements a practical method for modeling users in SIC turbo loop multiuser detection architectures, wherein in each loop unsubtracted estimation errors from previous loops are used to appropriately scale the error covariance matrix for each user, thereby accurately representing the remaining residual interference in the data stream for each desired user. The effect of estimation errors in previous interference cancellation operations is thereby minimized, and symbol estimations in successive turbo loops are improved, for example during multiuser MMSE, multiuser MMSE with interference rejection combining (MMSE-IRC), sample matrix inversion (SMI), or any of their adaptive variants (least mean-square, recursive least square, Kalman filter etc.). The estimated residual symbol energy can be computed per symbol, and then applied to entire data streams, to groups of symbols, or to each symbol separately.