Patent classifications
H04L25/03267
RECEIVER/TRANSMITTER CO-CALIBRATION OF VOLTAGE LEVELS IN PULSE AMPLITUDE MODULATION LINKS
A driver circuit of a PAM-N transmitting device transmits a PAM-N signal via a communication channel, wherein N is greater than 2, and the PAM-N signal has N signal levels corresponding to N symbols. A PAM-N receiving device receives the PAM-N signal. The PAM-N receiving device generates distortion information indicative of a level of distortion corresponding to inequalities in voltage differences between the N signal levels. The PAM-N receiving device transmits to the PAM-N transmitting device the distortion information indicative of the level of the distortion. The PAM-N transmitting device receives the distortion information. The PAM-N transmitting device adjusts one or more drive strength parameters of the driver circuit of the PAM-N transmitting device based on the distortion information.
DFE IMPLEMENTATION FOR WIRELINE APPLICATIONS
Disclosed embodiments include a decision feedback equalizer (DFE) comprising an N-bit parallel input adapted to be coupled to a communication channel and configured to receive consecutive communication symbols, a first DFE path including a first path input configured to receive communication symbols, and a first adder having a first adder input coupled to the first path input. There is a first DFE filter having outputs responsive to the first DFE filter inputs, the outputs coupled to the second adder input. The DFE includes a first path having a first slicer and a first multiplexer, a first path multiplexer output, and a second DFE path including a second path input configured to receive a second communication symbol, a second adder, a second DFE filter, a second slicer, and a second multiplexer.
Method and device for timing recovery decoupled FFE adaptation in SerDes receivers
A device and method for a receiver configured to perform timing recovery decoupled feed-forward equalizer (FFE) adaptation. The receiver device can include an analog front-end (AFE) device, which is coupled to a time-interleaved (TI) interface. The TI interface is coupled in a timing recovery feedback loop to FFE equalizers, a digital signal processor (DSP), a delay timing loop (DTL) device, and a clock device, which feeds back to the TI interface. The DSP has an additional pathway to the FFE equalizers, which has an additional pathway to the DTL device. The DTL loop is equipped with an interleave specific enable/disable vector Q[1:N] that can turn on/off the contribution of the specific time interleave errors to the timing recovery loop, which allows the FFE adaptation process to be decoupled from the timing recovery loop.
Power-efficient nonlinear equalizers and methods
One illustrative equalizer converts a receive signal into a sequence of symbol decisions using: a linear filter that filters the receive signal as part of deriving a first sequence of equalized signal samples; a first decision element that derives a tentative sequence of symbol decisions from the first sequence of equalized signal samples; a nonlinear filter that, when enabled, applies nonlinear compensation to the linearly filtered receive signal as part of deriving a second sequence of equalized signal samples; a second decision element that, when enabled, derives replacement symbol decisions from the second sequence of equalized signal samples; a subtraction element that calculates an equalization error for each symbol decision in the tentative sequence; and a controller that selectively enables the nonlinear filter and the second decision element to obtain a replacement symbol decision for each symbol decision in the tentative sequence having an equalization error greater than a predetermined value.
Programmable correlation computation system
Various embodiments described herein provide for a receiver device that includes a processor, a non-linear equalizer, an accumulation register, and a plurality of co-processors. Each of the plurality of co-processors is operably coupled to the processor, the non-linear equalizer, and the accumulation register. Each of the plurality of co-processors can be configured to receive a configuration value from the processor, receive a data signal for processing from the non-linear equalizer, process the data signal based on the configuration value, and provide at least a portion of the processed data signal to the processor.
Data receiving device and method
Provided are a data receiving device and a corresponding method for receiving the data. The data receiving device comprises a path control logic configured to store L symbol paths, where L is a natural number equal to or greater than 2, L feedback filters configured to calculate L inter-symbol interferences (ISI) for the L symbol paths, respectively, L operators configured to remove the L inter-symbol interferences from an output of a feed-forward equalizer, and a path metric calculator configured to receive outputs of the L operators and calculate a path metric for each of the L symbol paths, wherein the path control logic is configured to select L values among the calculated path metrics for the L symbol paths to update the L symbol paths.
LIVE OFFSET CANCELLATION OF THE DECISION FEEDBACK EQUALIZATION DATA SLICERS
A receiver utilizes loop-unrolled decision feedback equalization (DFE). For each sample, two comparators, each configured with different thresholds, sample an input signal. The output of one of these comparators is selected and used as the output of the receiver and may be optionally input to additional DFE circuitry. The output of the other (non-selected) comparator is used to adjust an input offset voltage of that same comparator. Adjustments to the offset voltages of the comparators may be based on a statistical analysis of the respective outputs of the two comparators when not selected. Adjustments to the offset voltages of the comparators may be based on comparisons between the respective outputs of the two comparators when not selected to the outputs of a reference comparator that has been calibrated for minimal or zero offset.
Devices and methods for parallelized recursive block decoding
A decoder for determining an estimate of a vector of information symbols carried by a signal received through a transmission channel represented by a channel matrix is provided. The decoder includes a block division unit configured to divide the vector of information symbols into two or more sub-vectors, each sub-vector being associated with a block level; two or more processors configured to determine, in parallel, candidate sub-vectors and to store the candidate sub-vectors in a first stack. Each processor is configured to determine at least a candidate sub-vector by applying a symbol estimation algorithm and to store each candidate sub-vector with a decoding metric and the block level associated with the candidate sub-vector. The decoding metric is lower than or equal to a decoding metric threshold. A processor among the two or more processors is configured to determine at least a candidate vector from candidate sub-vectors stored in the first stack, the candidate vector being associated with a cumulated decoding metric and to update the decoding metric threshold from the cumulated decoding metric.
Decision feedback equalizer and related control method
A decision feedback equalizer for generating an output signal according to an input signal includes: a feedforward equalizer, a feedback equalizer and a weight coefficient control unit. The feedforward equalizer includes a plurality of tapped delay lines and is controlled by a set of first weight coefficients. The feedback equalizer includes a plurality of tapped delay line and is controlled by a set of second weight coefficients. The weight coefficient control unit is employed to selectively adjust at least one of the set of first weight coefficients and determine a set of first boundary values for at least one of the set of second weight coefficients. When the at least one of the set of second weight coefficients does not exceed the set of first boundary values, the weight coefficient control unit increments the at least one of the set of first weight coefficients.
NON-UNIFORM QUANTIZED FEEDBACK IN FEDERATED LEARNING
Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a client device may determine a feedback associated with a machine learning component based at least in part on applying the machine learning component. Accordingly, the client device may transmit a quantized value based at least in part on the feedback. The quantized value is determined based at least in part on distances between the feedback and a non-uniform set of quantized digits. Numerous other aspects are provided.