A data stream processing device includes a plurality of data providing units, a plurality of processing units, and control circuitry. The data providing units are configured to output data values received via a plurality of data inputs, respectively. The processing units are configured to generate data outputs based on the data values, respectively. The control circuitry includes a mode selection input and is configured to simultaneously provide data values of different data streams to the data inputs of the data providing units, respectively, in response to the mode selection input receiving a signal indicating a first mode, and simultaneously provide a plurality of successive groups of data values of one of the data streams to the data inputs of the data providing units, respectively, in response to the mode selection input not receiving the signal indicating the first mode.

Surgical methods for stabilizing a joint are disclosed. The methods aid in surgical repairs by allowing for quick and reproducible repairs to be made. A bone tunnel is formed anteriorly/posteriorly in clavicle, and a bone tunnel is formed superiorly in acromion. At least one cannulated insert is provided into one or both of bone tunnels to protect the bone from abrasions caused by a flexible construct. A flexible construct is passed through the acromion tunnel and the clavicle tunnel. An attachment device may then be positioned on at least one side of the clavicle and/or acromion tunnel, and the flexible construct is attached to the attachment device.

A bus system according to the present disclosure includes: three or more devices that include one or a plurality of imaging devices, and transmit and receive a data signal in a time-division manner; and a bus to which the three or more devices are coupled and through which the data signal is transmitted. A first device of the three or more devices includes: an equalizer having a first operation mode in which a received signal is equalized with use of a coefficient set including one or a plurality of equalization coefficients, a storage unit that stores a plurality of the coefficient sets, and a communication controller that selects one of the plurality of the coefficient sets stored in the storage unit and causes the equalizer to operate in the first operation mode with use of the selected coefficient set.

A data stream processing device includes a plurality of data providing units, a plurality of processing units, and control circuitry. The data providing units are configured to output data values received via a plurality of data inputs, respectively. The processing units are configured to generate data outputs based on the data values, respectively. The control circuitry includes a mode selection input and is configured to simultaneously provide data values of different data streams to the data inputs of the data providing units, respectively, in response to the mode selection input receiving a signal indicating a first mode, and simultaneously provide a plurality of successive groups of data values of one of the data streams to the data inputs of the data providing units, respectively, in response to the mode selection input not receiving the signal indicating the first mode.

A signal processing circuit includes: a processor configured to adjust phases of reception samples which is supplied at a supply interval, according to a phase adjustment amount; and a processing circuit including a finite impulse response (FIR) filter with taps and configured to process, by the FIR filter, each of the reception samples and output output symbols at an output interval different from the supply interval, the processor is configured to: derive initial values of tap coefficients for the respective taps; and derive the phase adjustment amount such that a center of centroids of the tap coefficients at respective output time points of the output symbols coincides with a center of a number of taps of the FIR filter, the tap coefficients at respective output time points of the output symbols being set according to a deviation between the supply interval and the output interval and the initial values.

A reception device for receiving a data signal representing a data value 0 or 1. The reception device includes an equalizer circuit and a control circuit. The equalizer circuit outputs an output value representing a result obtained by comparing a voltage based on the received data signal and a first voltage as a reference, at each clock timing corresponding to the data signal. The control circuit is connected to the equalizer circuit. The control circuit changes, before the data signal is received, a tap coefficient related to a characteristic of the equalizer circuit in a state in which a second voltage different from the first voltage, instead of the voltage of the data signal, is supplied to the equalizer circuit, to detect an inverted tap coefficient that is the tap coefficient at a boundary where a data value of the output value is inverted. The control circuit sets the inverted tap coefficient to the equalizer circuit at a time of receiving the data signal.

According to one embodiment, an equalizer circuit includes a nonlinear equalizer including: a determination circuit configured to generate a second signal indicating a digital value of a first signal, based on a first clock signal; a clock generation circuit configured to generate a second clock signal having a time constant of a falling edge larger than a time constant of a rising edge, based on the first clock signal; and a feedback circuit configured to generate a third signal by feeding back the second signal to the first signal, based on the second clock signal.

According to one embodiment, an equalizer circuit includes a nonlinear equalizer including: a determination circuit configured to generate a second signal indicating a digital value of a first signal, based on a first clock signal; a clock generation circuit configured to generate a second clock signal having a time constant of a falling edge larger than a time constant of a rising edge, based on the first clock signal; and a feedback circuit, configured to generate a third signal by feeding back the second signal to the first signal, based on the second clock signal.

A signal processing circuit includes: a processor configured to adjust phases of reception samples which is supplied at a supply interval, according to a phase adjustment amount; and a processing circuit including a finite impulse response (FIR) filter with taps and configured to process, by the FIR filter, each of the reception samples and output output symbols at an output interval different from the supply interval, the processor is configured to: derive initial values of tap coefficients for the respective taps; and derive the phase adjustment amount such that a center of centroids of the tap coefficients at respective output time points of the output symbols coincides with a center of a number of taps of the FIR filter, the tap coefficients at respective output time points of the output symbols being set according to a deviation between the supply interval and the output interval and the initial values.

A driver circuit includes a feed-forward equalization (FFE) circuit. The FFE circuit receives a plurality of pulse-amplitude modulation (PAM) symbol values to be transmitted at one of multiple PAM levels. The FFE circuit includes a first partial lookup table, one or more additional partial lookup tables, and an adder circuit. The first partial lookup table contains partial finite impulse-response (FIR) values and indexed based on a current PAM symbol value, a precursor PAM symbol value, and a postcursor PAM symbol value. The one or more additional partial lookup tables each contain partial FIR values and indexed based on a respective additional one or more of the PAM symbol values. The adder circuit adds results of lookups from the first partial lookup table and the additional partial lookup tables to produce an output value.