The present invention is directed to communication systems and methods thereof. More specifically, an embodiment of the present invention includes a buffer that is coupled to a reference terminal. A shift register stores decision levels for post-cursor positions. A plurality of switches converts the decision levels to equalization currents during an equalization process. The equalization currents are converted to equalization voltage terms by one or more load resistors. The buffer is provided between the reference terminal and the one or more load resistors. There are other embodiments as well.

A receiver (e.g., for a 10 G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decorder, for example, a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm.

A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

A receiver (e.g., for a 10G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decoder, for example a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm.

Techniques to manage dwell times for pilot rotation are described. An apparatus may comprise a memory configured to store a data structure with a set of modulation and coding schemes (MCS) available to an orthogonal frequency division multiplexing (OFDM) system, each MCS having an associated pilot dwell time. The apparatus may further comprise a processor circuit coupled to the memory, the processor circuit configured to identify a MCS to communicate a packet using multiple subcarriers of the OFDM system, and retrieve a pilot dwell time associated with the MCS from the memory, the pilot dwell time to indicate when to shift a pilot tone between subcarriers of the multiple subcarriers during communication of the packet. Other embodiments are described and claimed.

A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.

A receiver (e.g., for a 10G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decoder, for example a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm.

Techniques to manage dwell times for pilot rotation are described. An apparatus may comprise a memory configured to store a data structure with a set of modulation and coding schemes (MCS) available to an orthogonal frequency division multiplexing (OFDM) system, each MCS having an associated pilot dwell time. The apparatus may further comprise a processor circuit coupled to the memory, the processor circuit configured to identify a MCS to communicate a packet using multiple subcarriers of the OFDM system, and retrieve a pilot dwell time associated with the MCS from the memory, the pilot dwell time to indicate when to shift a pilot tone between subcarriers of the multiple subcarriers during communication of the packet. Other embodiments are described and claimed.

In a coherent optical receiver receiving a polarization multiplexed optical signal through an optical communications network, a method of compensating noise due to polarization dependent loss (PDL). A Least Mean Squares (LMS) compensation block processes sample streams of the received optical signal to generate symbol estimates of symbols modulated onto each transmitted polarization of the optical signal. A decorrelation block de-correlates noise in the respective symbol estimates of each transmitted polarization and generating a set of decorrelated coordinate signals. A maximum likelihood estimator soft decodes the de-correlated coordinate signals generated by the decorrelation block.

Disclosed are apparatuses, systems, and techniques for deploying and training machine learning models for fast and efficient equalization of signals transmitted over communication channels. In one embodiment, the techniques include processing, using first model(s), a digital representation of a received (RX), via a communication channel, signal to obtain channel loss metrics representative of a difference between the RX signal and a transmitted (TX) signal. The techniques further include obtaining a first set of equalization (EQ) parameter(s), and iteratively obtaining a second set of EQ parameter(s). The techniques further include configuring, using the second set of the EQ parameters, one or more EQ circuits to equalize at least one of the RX signal, the TX signal, or a channel signal.