Low dielectric organosilicon films are deposited by a process comprising the steps of: providing a substrate within a vacuum chamber; introducing into the vacuum chamber a gaseous silicon containing precursor composition comprising at least one organosilicon precursor selected from the group consisting of Formula (I) and Formula (II): ##STR00001## wherein, R.sub.1, R.sub.2, R.sub.3, R.sub.4, R.sub.5, and R.sub.6 are as defined herein, and applying energy to the gaseous structure forming composition in the vacuum chamber to induce reaction of the at least one organosilicon precursor to deposit a film on at least a portion of the substrate.

Passivation layers to inhibit vapor deposition can be used on reactor surfaces to minimize deposits while depositing on a substrate housed therein, or on particular substrate surfaces, such as metallic surfaces on semiconductor substrates to facilitate selective deposition on adjacent dielectric surfaces. Passivation agents that are smaller than typical self-assembled monolayer precursors can have hydrophobic or non-reactive ends and facilitate more dense passivation layers more quickly than self-assembled monolayers, particularly over complex three-dimensional structures.

A semiconductor device includes: a semiconductor layer; a first insulating film which covers a surface of the semiconductor layer; a first adhering film which is formed on a surface of the first insulating film and contains a carbonyl group; and a second insulating film which covers a surface of the first adhering film and has a lower dielectric constant than the first insulating film.

A modified trench metal-semiconductor alloy formation method involves depositing a layer of a printable dielectric or a sacrificial carbon material within a trench structure and over contact regions of a semiconductor device, and then selectively removing the printable dielectric or sacrificial carbon material to segment the trench and form plural contact vias. A metallization layer is formed within the contact vias and over the contact regions.

A semiconductor device includes: a semiconductor layer; a first insulating film which covers a surface of the semiconductor layer; a first adhering film which is formed on a surface of the first insulating film and contains a carbonyl group; and a second insulating film which covers a surface of the first adhering film and has a lower dielectric constant than the first insulating film.

A composition for planarizing a semiconductor device surface includes poly(methyl silsesquioxane) resin, at least one of a quaternary ammonium salt and an aminopropyltriethoxysilane salt, and at least one solvent. The poly(methyl silsesquioxane) resin ranges from 1 wt. % to 40 wt. % of the composition. The poly(methyl silsesquioxane) resin has a weight average molecular weight between 500 Da and 5,000 Da. The at least one of the quaternary ammonium salt and the aminopropyltriethoxysilane salt ranges from 0.01 wt. % to 0.20 wt. % of the composition. The at least one solvent comprises the balance of the composition.

Low dielectric materials and films comprising same have been identified for improved performance when used as interlevel dielectrics in integrated circuits as well as methods for making same.

Semiconductor devices and manufacturing method of the same are disclosed. A semiconductor device includes a substrate, a p-type MOS transistor, an n-type MOS transistor and a cured flowable oxide layer. The substrate includes a first region and a second region. The p-type MOS transistor is in the first region. The n-type MOS transistor is in the second region. The cured flowable oxide layer covers the p-type MOS transistor and the n-type MOS transistor, wherein a first strain of the cured flowable oxide layer applying to the p-type MOS transistor is different from a second strain of the cured flowable oxide layer applying to the n-type MOS transistor, and the difference therebetween is greater than 0.002 Gpa.

A modified trench metal-semiconductor alloy formation method involves depositing a layer of a printable dielectric or a sacrificial carbon material within a trench structure and over contact regions of a semiconductor device, and then selectively removing the printable dielectric or sacrificial carbon material to segment the trench and form plural contact vias. A metallization layer is formed within the contact vias and over the contact regions.

A modified trench metal-semiconductor alloy formation method involves depositing a layer of a printable dielectric or a sacrificial carbon material within a trench structure and over contact regions of a semiconductor device, and then selectively removing the printable dielectric or sacrificial carbon material to segment the trench and form plural contact vias. A metallization layer is formed within the contact vias and over the contact regions.