Provided is a capacitor that has good bonding between the dielectric layer and the conductive layer, has a characteristic of low ESR, and keeps leak current suppressed. The capacitor contains a dielectric layer and a conductive film and is characterized in that the dielectric layer contains an organic compound and a metal compound and that the conductive film contains a conductive material and an organic compound.

A device includes a semiconductor fin and a shallow trench isolation (STI) structure. The semiconductor fin extends from a semiconductor substrate. The STI structure is around a lower portion of the semiconductor fin, and the STI structure includes a liner layer and an isolation material. The liner layer includes a metal-contained ternary dielectric material. The isolation material is over the liner layer.

Methods for forming a metal silicate film on a substrate in a reaction chamber by a cyclical deposition process are provided. The methods may include: regulating the temperature of a hydrogen peroxide precursor below a temperature of 70 C. prior to introduction into the reaction chamber, and depositing the metal silicate film on the substrate by performing at least one unit deposition cycle of a cyclical deposition process. Semiconductor device structures including a metal silicate film formed by the methods of the disclosure are also provided.

An example embodiment of the present disclosure involves a method for semiconductor device fabrication. The method comprises providing a structure that includes a conductive component and an interlayer dielectric (ILD) that includes silicon and surrounds the conductive component, and forming, over the conductive component and the ILD, an etch stop layer (ESL) that includes metal oxide. The ESL includes a first portion in contact with the conductive component and a second portion in contact with the ILD. The method further comprises baking the ESL to transform the metal oxide located in the second portion of the ESL into metal silicon oxide, and selectively etching the ESL so as to remove the first portion of the ESL but not the second portion of the ESL.

A device includes a semiconductor substrate, a gate stack, and an interlayer dielectric. The gate stack is over the semiconductor substrate. The interlayer dielectric is over the semiconductor substrate and surrounds the gate stack. The interlayer dielectric includes a liner layer and a filling layer. The liner layer lines the gate stack. The filling layer is over the liner layer and includes a metal-contained ternary dielectric material.

A method includes removing a dummy gate stack to form a trench between gate spacers, depositing a gate dielectric extending into the trench, and performing a first treatment process on the gate dielectric. The first treatment process is performed using a fluorine-containing gas. A first drive-in process is then performed to drive fluorine in the fluorine-containing gas into the gate dielectric. The method further includes performing a second treatment process on the gate dielectric, wherein the second treatment process is performed using the fluorine-containing gas, and performing a second drive-in process to drive fluorine in the fluorine-containing gas into the gate dielectric. After the second drive-in process, conductive layers are formed to fill the trench.

A method for depositing an oxide film on a substrate by a cyclical deposition is disclosed. The method may include: depositing a metal oxide film over the substrate utilizing at least one deposition cycle of a first sub-cycle of the cyclical deposition process; and depositing a silicon oxide film directly on the metal oxide film utilizing at least one deposition cycle of a second sub-cycle of the cyclical deposition process. Semiconductor device structures including an oxide film deposited by the methods of the disclosure are also disclosed.

A laminated body of an embodiment includes: a silicon layer; a first beryllium oxide layer on the silicon layer; and a diamond semiconductor layer on the first beryllium oxide layer.

A method for fabricating an interconnection structure includes providing a substrate, forming a dielectric layer on the substrate, forming a conductive structure in the dielectric layer, forming a cap layer doped with silicon on the conductive structure and the dielectric layer, and performing an annealing process on the conductive structure and the cap layer. During the annealing process, the silicon ions in the cap layer react with the material of the conductive structure and form chemical bonds. As such, the connection strength between the cap layer and the conductive structure is improved, which is conducive to suppressing electro migration in the formed interconnection structure. Therefore, the reliability of the formed interconnection structure is improved.

A method of producing an electron emitting device includes: step A of providing an aluminum substrate or providing an aluminum layer supported by a substrate; step B of anodizing a surface of the aluminum substrate or a surface of the aluminum layer to form a porous alumina layer having a plurality of pores; step C of applying Ag nanoparticles in the plurality of pores to allow the Ag nanoparticles to be supported in the plurality of pores; step D of, after step C, applying a dielectric layer-forming solution onto substantially the entire surface of the aluminum substrate or the aluminum layer, the dielectric layer-forming solution containing, in an amount of not less than 7 mass % but less than 20 mass %, a polymerization product having siloxane bonds; step E of, after step D, at least reducing a solvent contained in the dielectric layer-forming solution to form the dielectric layer; and step F of forming an electrode on the dielectric layer.