A method for fabricating a semiconductor structure includes forming a semiconductor layer over a substrate and forming an aluminum-silicon nitride layer upon the semiconductor layer. When the semiconductor layer in particular comprises a III-V semiconductor material such as a group III nitride semiconductor material or a gallium nitride semiconductor material, the aluminum-silicon nitride material provides a superior passivation in comparison with a silicon nitride material.

There is provided a semiconductor device comprising a group III nitride semiconductor layer; a gate insulating film formed on the group III nitride semiconductor layer; and a gate electrode formed on the gate insulating film. The gate insulating film comprises a first film that is placed on the group III nitride semiconductor layer, includes silicon and has a higher crystallization temperature than a crystallization temperature of aluminum oxide; and a second film that is placed on the first film and contains aluminum oxide. The first film has a hydrogen concentration of not lower than 110.sup.21 atoms/cm.sup.3, a nitrogen concentration of not lower than 110.sup.19 atoms/cm.sup.3 and a carbon concentration of not lower than 110.sup.19 atoms/cm.sup.3. This configuration prevents crystallization of aluminum oxide.

A method for fabricating an interconnection structure includes providing a substrate, forming a dielectric layer on the substrate, forming a conductive structure in the dielectric layer, forming a cap layer doped with silicon on the conductive structure and the dielectric layer, and performing an annealing process on the conductive structure and the cap layer. During the annealing process, the silicon ions in the cap layer react with the material of the conductive structure and form chemical bonds. As such, the connection strength between the cap layer and the conductive structure is improved, which is conducive to suppressing electro migration in the formed interconnection structure. Therefore, the reliability of the formed interconnection structure is improved.

Interconnect structures and methods of formation of such interconnect structures are provided herein. In some embodiments, a method of forming an interconnect includes: depositing a silicon-aluminum oxynitride (SiAlON) layer atop a first layer of a substrate, wherein the first layer comprises a first feature filled with a first conductive material; depositing a dielectric layer over the silicon-aluminum oxynitride (SiAlON) layer; and forming a second feature in the dielectric layer and the silicon-aluminum oxynitride (SiAlON) layer to expose the first conductive material.

Provided is a method of manufacturing a semiconductor device according to the present invention, a ring-shaped electrode plate 18 with an opening having a diameter smaller than a diameter of a semiconductor wafer W is disposed between a first electrode plate 14 and a second electrode plate 16, the semiconductor wafer W is arranged between the ring-shaped electrode plate 18 and the second electrode plate 16, and a glass film is formed on a glass film forming scheduled surface in a state where a potential lower than a potential V2 of the second electrode plate 16 is applied to the ring-shaped electrode plate 18. According to the method of manufacturing a semiconductor device of the present invention, even when the glass film forming step is performed using the semiconductor wafer where the base insulating film is formed on the glass film forming scheduled surface as the semiconductor wafer, lowering of deposition efficiency of fine glass particles on the outer peripheral portion of the semiconductor wafer can be suppressed and hence, highly reliable semiconductor devices can be manufactured with high productivity.

There is provided a semiconductor device comprising a group III nitride semiconductor layer; a gate insulating film formed on the group III nitride semiconductor layer; and a gate electrode formed on the gate insulating film. The gate insulating film comprises a first film that is placed on the group III nitride semiconductor layer, includes silicon and has a higher crystallization temperature than a crystallization temperature of aluminum oxide; and a second film that is placed on the first film and contains aluminum oxide.

The first film has a hydrogen concentration of not lower than 110.sup.21 atoms/cm.sup.3, a nitrogen concentration of not lower than 110.sup.19 atoms/cm.sup.3 and a carbon concentration of not lower than 110.sup.19 atoms/cm.sup.3. This configuration prevents crystallization of aluminum oxide.

Dielectric composite films characterized by a dielectric constant (k) of less than about 7 and having a density of at least about 2.5 g/cm.sup.3 are deposited on partially fabricated semiconductor devices to serve as etch stop layers. The composite films in one embodiment include at least two elements selected from the group consisting of Al, Si, and Ge, and at least one element selected from the group consisting of O, N, and C. In one embodiment the composite film includes Al, Si and O. In one implementation, a substrate containing an exposed dielectric layer (e.g., a ULK dielectric) and an exposed metal layer is contacted with an aluminum-containing compound (such as trimethylaluminum) and, sequentially, with a silicon-containing compound. Adsorbed compounds are then treated with an oxygen-containing plasma (e.g., plasma formed in a CO.sub.2-containing gas) to form a film that contains Al, Si, and O.

A nitride light-emitting diode (LED) fabrication method includes: providing a glass substrate; stacking a buffer layer structure composed of circular SiAlN layers and AlGaN layers with the number of cycles 1-5; growing a non-doped GaN layer, an N-type layer, a quantum well layer and a P-type layer. By using the low-cost glass the substrate that has a mature processing technology, and growing a SiAlN and an AlGaN buffer layer thereon, lattice mismatch constant between the substance and the epitaxial layer can be improved. Therefore, photoelectric property of the LED can be improved.

A method and apparatus for filling one or more gaps created during manufacturing of a feature on a substrate by: providing a bottom area of a surface of the one or more gaps with a first reactant; providing a second reactant to the substrate; and, allowing the first reactant to initiate reaction of the second reactant in the bottom area of the surface in a stoichiometric ratio of one molecule of the first reactant to multiple molecules of the second reactants leaving a top area of the surface of the one or more gaps which was not provided with the first reactant initially substantially empty.

An example embodiment of the present disclosure involves a method for semiconductor device fabrication. The method comprises providing a structure that includes a conductive component and an interlayer dielectric (ILD) that includes silicon and surrounds the conductive component, and forming, over the conductive component and the ILD, an etch stop layer (ESL) that includes metal oxide. The ESL includes a first portion in contact with the conductive component and a second portion in contact with the ILD. The method further comprises baking the ESL to transform the metal oxide located in the second portion of the ESL into metal silicon oxide, and selectively etching the ESL so as to remove the first portion of the ESL but not the second portion of the ESL.