A method includes forming a gate stack of a transistor. The formation of the gate stack includes forming a silicon oxide layer on a semiconductor region, depositing a hafnium oxide layer over the silicon oxide layer, depositing a lanthanum oxide layer over the hafnium oxide layer, and depositing a work-function layer over the lanthanum oxide layer. Source/drain regions are formed on opposite sides of the gate stack.

A ferroelectric semiconductor device and method are described herein. The method includes performing a diffusion anneal process to drive elements of a dopant film through an amorphous silicon layer and into a gate dielectric layer over a fin to form a doped gate dielectric layer with a gradient depth profile of dopant concentrations. The doped gate dielectric layer is crystallized during a post-cap anneal process to form a gradient depth profile of ferroelectric properties within the crystallized gate dielectric layer. A metal gate electrode is formed over the crystallized gate dielectric layer to obtain a ferroelectric transistor with multi-ferroelectric properties between the gate electrode and the channel. The ferroelectric transistor may be used in deep neural network (DNN) applications.

The first gate insulating film is an insulating film made of silicon oxide, and to which hafnium (Hf) is added without addition of aluminum (Al). Also, the second gate insulating film is an insulating film made of silicon oxide, and to which aluminum is added without addition of hafnium. The third gate insulating film is an insulating film made of silicon oxide, and to which aluminum is added. Further, the fourth gate insulating film is an insulating film made of silicon oxide, and to which hafnium is added. Accordingly, it is possible to reduce the power consumption of the semiconductor device.

A semiconductor device including an oxide-nitride-oxide (ONO) structure having a multi-layer charge storing layer and methods of forming the same are provided. Generally, the method involves: (i) forming a first oxide layer of the ONO structure; (ii) forming a multi-layer charge storing layer comprising nitride on a surface of the first oxide layer; and (iii) forming a second oxide layer of the ONO structure on a surface of the multi-layer charge storing layer. Preferably, the charge storing layer comprises at least two silicon oxynitride layers having differing stochiometric compositions of Oxygen, Nitrogen and/or Silicon. More preferably, the ONO structure is part of a silicon-oxide-nitride-oxide-silicon (SONOS) structure and the semiconductor device is a SONOS memory transistor. Other embodiments are also disclosed.

Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin on a substrate, a second fin on the substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes an insulating liner and a fill material on the insulating liner. The insulating liner abuts a first sidewall of the first fin and a second sidewall of the second fin. The insulating liner includes a material with a band gap greater than 5 eV.

An example embodiment of the present disclosure involves a method for semiconductor device fabrication. The method comprises providing a structure that includes a conductive component and an interlayer dielectric (ILD) that includes silicon and surrounds the conductive component, and forming, over the conductive component and the ILD, an etch stop layer (ESL) that includes metal oxide. The ESL includes a first portion in contact with the conductive component and a second portion in contact with the ILD. The method further comprises baking the ESL to transform the metal oxide located in the second portion of the ESL into metal silicon oxide, and selectively etching the ESL so as to remove the first portion of the ESL but not the second portion of the ESL.

Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin on a substrate, a second fin on the substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes an insulating liner and a fill material on the insulating liner. The insulating liner abuts a first sidewall of the first fin and a second sidewall of the second fin. The insulating liner includes a material with a band gap greater than 5 eV.

A method includes forming a gate stack of a transistor. The formation of the gate stack includes forming a silicon oxide layer on a semiconductor region, depositing a hafnium oxide layer over the silicon oxide layer, depositing a lanthanum oxide layer over the hafnium oxide layer, and depositing a work-function layer over the lanthanum oxide layer. Source/drain regions are formed on opposite sides of the gate stack.

The performances of a semiconductor device of a memory element are improved. Over a semiconductor substrate, a gate electrode for memory element is formed via overall insulation film of gate insulation film for memory element. The overall insulation film has first insulation film, second insulation film over first insulation film, third insulation film over second insulation film, fourth insulation film over third insulation film, and fifth insulation film over fourth insulation film. The second insulation film is an insulation film having charge accumulation function. Each band gap of first insulation film and third insulation film is larger than the band gap of second insulation film. The third insulation film is polycrystal film including high dielectric constant material containing metallic element and oxygen. Fifth insulation film is polycrystal film including the same material as that for third insulation film. Fourth insulation film includes different material from that for third insulation film.

The performances of a semiconductor device of a memory element are improved. Over a semiconductor substrate, a gate electrode for memory element is formed via overall insulation film of gate insulation film for memory element. The overall insulation film has first insulation film, second insulation film over first insulation film, third insulation film over second insulation film, fourth insulation film over third insulation film, and fifth insulation film over fourth insulation film. The second insulation film is an insulation film having charge accumulation function. Each band gap of first insulation film and third insulation film is larger than the band gap of second insulation film. The third insulation film is polycrystal film including high dielectric constant material containing metallic element and oxygen. Fifth insulation film is polycrystal film including the same material as that for third insulation film. Fourth insulation film includes different material from that for third insulation film.