In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region, a first conductive layer is formed over the gate dielectric layer, a shield layer is formed over the first conductive layer forming a bilayer structure, a capping layer is formed over the shield layer, a first annealing operation is performed after the capping layer is formed, the capping layer is removed after the first annealing operation, and a gate electrode layer is formed after the capping layer is removed.

Provided is a capacitor that has good bonding between the dielectric layer and the conductive layer, has a characteristic of low ESR, and keeps leak current suppressed. The capacitor contains a dielectric layer and a conductive film and is characterized in that the dielectric layer contains an organic compound and a metal compound and that the conductive film contains a conductive material and an organic compound.

A method for forming a gate structure includes forming a trench within an interlayer dielectric layer (ILD) that is disposed on a semiconductor substrate, the trench exposing a top surface of the semiconductor substrate, forming an interfacial layer at a bottom of the trench, forming a dielectric layer within the trench, forming a work function metal layer on the dielectric layer, forming an in-situ nitride layer on the work function metal layer in the trench, performing a first cobalt deposition process to form a cobalt layer within the trench, performing a second cobalt deposition process to increase a thickness of the cobalt layer within the trench, and performing an electrochemical plating (ECP) process to fill the trench with cobalt.

An example embodiment of the present disclosure involves a method for semiconductor device fabrication. The method comprises providing a structure that includes a conductive component and an interlayer dielectric (ILD) that includes silicon and surrounds the conductive component, and forming, over the conductive component and the ILD, an etch stop layer (ESL) that includes metal oxide. The ESL includes a first portion in contact with the conductive component and a second portion in contact with the ILD. The method further comprises baking the ESL to transform the metal oxide located in the second portion of the ESL into metal silicon oxide, and selectively etching the ESL so as to remove the first portion of the ESL but not the second portion of the ESL.

A method includes removing a dummy gate stack to form a trench between gate spacers, depositing a gate dielectric extending into the trench, and performing a first treatment process on the gate dielectric. The first treatment process is performed using a fluorine-containing gas. A first drive-in process is then performed to drive fluorine in the fluorine-containing gas into the gate dielectric. The method further includes performing a second treatment process on the gate dielectric, wherein the second treatment process is performed using the fluorine-containing gas, and performing a second drive-in process to drive fluorine in the fluorine-containing gas into the gate dielectric. After the second drive-in process, conductive layers are formed to fill the trench.

A film forming method includes: preparing a substrate having a surface on which a first film containing boron and a second film made of a material different from that of the first film are formed; supplying a raw material gas, which contains halogen and an element X other than halogen, to the surface of the substrate; and supplying a plasmarized reaction gas, which contains oxygen, to the surface of the substrate, wherein a third film as an oxide film of the element X is selectively formed on the second film with respect to the first film by alternately supplying the raw material gas and the plasmarized reaction gas.

There is provided a process of forming a film containing a metal element, an additional element different from the metal element and at least one of nitrogen and carbon on a substrate by performing a cycle a predetermined number of times, the cycle including non-simultaneously performing: (a) supplying a first precursor gas containing the metal element and a second precursor gas containing the additional element to the substrate so that supply periods of the first precursor gas and the second precursor gas at least partially overlap with each other; and (b) supplying a reaction gas containing the at least one of nitrogen and carbon to the substrate.

A method for forming a gate structure includes forming a trench within an interlayer dielectric layer (ILD) that is disposed on a semiconductor substrate, the trench exposing a top surface of the semiconductor substrate, forming an interfacial layer at a bottom of the trench, forming a dielectric layer within the trench, forming a work function metal layer on the dielectric layer, forming an in-situ nitride layer on the work function metal layer in the trench, performing a first cobalt deposition process to form a cobalt layer within the trench, performing a second cobalt deposition process to increase a thickness of the cobalt layer within the trench, and performing an electrochemical plating (ECP) process to fill the trench with cobalt.

Methods of forming and processing semiconductor devices are described. Certain embodiments related to electronic devices which comprise a dipole region having an interlayer dielectric, a high-? dielectric material, and a dipole layer. The dipole layer comprises one or more of titanium aluminum nitride (TiAlN), titanium tantalum nitride (TiTaN), titanium oxide (TiO), tantalum oxide (TaO), and titanium aluminum carbide (TiAlC).

Methods for forming a titanium-containing hard mask film on a substrate surface by exposing the substrate surface to a titanium-containing precursor. The titanium-containing hard mask comprises one or more of silicon, oxygen or carbon atoms and, optionally, nitrogen atoms.