Patent classifications
H01L21/02159
Semiconductor Fin Cutting Process and Structures Formed Thereby
Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin on a substrate, a second fin on the substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes an insulating liner and a fill material on the insulating liner. The insulating liner abuts a first sidewall of the first fin and a second sidewall of the second fin. The insulating liner includes a material with a band gap greater than 5 eV.
Semiconductor Fin cutting process and structures formed thereby
Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin on a substrate, a second fin on the substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes an insulating liner and a fill material on the insulating liner. The insulating liner abuts a first sidewall of the first fin and a second sidewall of the second fin. The insulating liner includes a material with a band gap greater than 5 eV.
Volume-less Fluorine Incorporation Method
A method includes removing a dummy gate stack to form a trench between gate spacers, depositing a gate dielectric extending into the trench, and performing a first treatment process on the gate dielectric. The first treatment process is performed using a fluorine-containing gas. A first drive-in process is then performed to drive fluorine in the fluorine-containing gas into the gate dielectric. The method further includes performing a second treatment process on the gate dielectric, wherein the second treatment process is performed using the fluorine-containing gas, and performing a second drive-in process to drive fluorine in the fluorine-containing gas into the gate dielectric. After the second drive-in process, conductive layers are formed to fill the trench.
Semiconductor Fin cutting process and structures formed thereby
Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin on a substrate, a second fin on the substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes an insulating liner and a fill material on the insulating liner. The insulating liner abuts a first sidewall of the first fin and a second sidewall of the second fin. The insulating liner includes a material with a band gap greater than 5 eV.
Semiconductor structure and its formation method
Embodiments of the present application provide a semiconductor structure and its formation method. The method includes: the substrate being provided with a groove, a sidewall of the groove including a first sub-sidewall and a second sub-sidewall that extend upwards from a bottom of the groove sub-sidewall; blowing a first precursor to a surface of the substrate, so that the first precursor is attached to a top surface of the substrate and the second sub-sidewall; blowing a second precursor to the surface of the substrate, so that the second precursor reacts with the first precursor to form a dielectric layer; alternately blowing the first precursor and the second precursor to the surface of the substrate to form a plurality of dielectric layers until a top opening of the groove is blocked, a region enclosed by the first sub-sidewall, the dielectric layer and the bottom of the groove forming a void.
Interface engineering for high capacitance capacitor for liquid crystal display
Embodiments of the disclosure generally provide methods of forming a capacitor with high capacitance and low leakage as well as a good interface control for thin film transistor (TFT) applications. In one embodiment, a thin film transistor structure includes a capacitor formed in a thin film transistor device. The capacitor further includes a common electrode disposed on a substrate, a dielectric layer formed on the common electrode and a pixel electrode formed on the dielectric layer. An interface protection layer formed between the common electrode and the dielectric layer, or between the dielectric layer and the pixel electrode. A gate insulating layer fabricated by a high-k material may also be utilized in the thin film transistor structure.
SEMICONDUCTOR STRUCTURE CUTTING PROCESS AND STRUCTURES FORMED THEREBY
Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin on a substrate, a second fin on the substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes an insulating liner and a fill material on the insulating liner. The insulating liner abuts a first sidewall of the first fin and a second sidewall of the second fin. The insulating liner includes a material with a band gap greater than 5 eV.
METHODS AND APPLICATIONS OF NOVEL AMORPHOUS HIGH-K METAL-OXIDE DIELECTRICS BY SUPER-CYCLE ATOMIC LAYER DEPOSITION
Embodiments of the disclosure relate to articles and transistor structures and methods of preparation and use thereof, including a substrate and an amorphous oxide film overlaying at least a portion of the substrate, where the amorphous oxide film includes a first oxide and a second oxide. The first oxide can include zirconium oxide (ZrO.sub.2), hafnium oxide (HfO.sub.2) or a combination thereof, the second oxide can include silicon dioxide (SiO.sub.2), aluminum oxide (Al.sub.2O.sub.3), nitric oxide (NO) or combinations thereof. The amorphous oxide film can conformal and have a porosity of less than about 1% and may have a dielectric constant (k) of about 8 to about 28.
Method of forming dielectric films, new precursors and their use in semiconductor manufacturing
Method of deposition on a substrate of a dielectric film by introducing into a reaction chamber a vapor of a precursor selected from the group consisting of Zr(MeCp)(NMe.sub.2).sub.3, Zr(EtCp)(NMe.sub.2).sub.3, ZrCp(NMe.sub.2).sub.3, Zr(MeCp)(NEtMe).sub.3, Zr(EtCp)(NEtMe).sub.3, ZrCp(NEtMe).sub.3, Zr(MeCp)(NEt.sub.2).sub.3, Zr(EtCp)(NEt.sub.2).sub.3, ZrCp(NEt.sub.2).sub.3, Zr(iPr.sub.2Cp)(NMe.sub.2).sub.3, Zr(tBu.sub.2Cp)(NMe.sub.2).sub.3, Hf(MeCp)(NMe.sub.2).sub.3, Hf(EtCp)(NMe.sub.2).sub.3, HfCp(NMe.sub.2).sub.3, Hf(MeCp)(NEtMe).sub.3, Hf(EtCp)(NEtMe).sub.3, HfCp(NEtMe).sub.3, Hf(MeCp)(NEt.sub.2).sub.3, Hf(EtCp)(NEt.sub.2).sub.3, HfCp(NEt.sub.2).sub.3, Hf(iPr.sub.2Cp)(NMe.sub.2).sub.3, Hf(tBu.sub.2Cp)(NMe.sub.2).sub.3, and mixtures thereof; and depositing the dielectric film on the substrate.
Semiconductor Fin Cutting Process and Structures Formed Thereby
Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin on a substrate, a second fin on the substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes an insulating liner and a fill material on the insulating liner. The insulating liner abuts a first sidewall of the first fin and a second sidewall of the second fin. The insulating liner includes a material with a band gap greater than 5 eV.