Provided is an electronic device including a first lower material film, a first upper material film on the first lower material film, a first two-dimensional electron gas between the first lower material film and the first upper material film, a second lower material film on the first upper material film, a second upper material film on the second lower material film, a second two-dimensional electron gas between the second lower material film and the second upper material film, a source electrode on the second upper material film, a drain electrode on the second upper material film, a gate insulating film on the second upper material film, and a gate electrode on the gate insulating film.

A porous thin film includes a framework that includes a plurality of pores. The pores extend from an opening located at an upper surface of the framework to a bottom surface contained in the framework. A pore-coating film is formed on sidewalls and the bottom surface of the pores.

A method for depositing, patterning and removing a layer of aluminum oxide as a masking material layer for performing a deep, high-aspect ratio etches into a substrate. The method comprising deposing a photoresist onto the substrate, performing lithography processing on the photoresist, developing the photoresist to pattern the photoresist into a mask design, depositing a thin-film layer of aluminum oxide; immersing the substrate into a solution to lift-off the aluminum oxide in regions where the aluminum oxide is deposited on top of the photoresist thereby leaving the patterned aluminum oxide layer on the substrate where no photoresist was present, performing deep reactive ion etching on the substrate wherein the hard masking material layer composed of aluminum oxide functions as a protective masking layer on the substrate to prevent etching from occurring where the aluminum oxide is present, and removing the aluminum oxide masking layer by immersion in a solution.

A method for forming a foreign oxide or foreign nitride layer (6) on a substrate (1) of a semiconductor comprises providing a semiconductor substrate (1) having an oxidized or nitridized surface layer (3), supplying a foreign element (5) on the oxidized or nitridized surface layer; and keeping the oxidized or nitridized surface layer (3) at an elevated temperature so as to oxidize or nitridize at least partially the foreign element by the oxygen or nitrogen, respectively, initially present in the oxidized or nitridized surface layer (3).

A semiconductor device including a barrier layer surrounding a work function metal layer and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate; a first channel region over the semiconductor substrate; a second channel region over the first channel region; gate dielectric layers surrounding the first channel region and the second channel region; work function metal layers surrounding the gate dielectric layers; and barrier layers surrounding the work function metal layers, a first barrier layer surrounding the first channel region being merged with a second barrier layer surrounding the second channel region.

The present disclosure describes epitaxial oxide field effect transistors (FETs). In some embodiments, a FET comprises: a substrate comprising an oxide material; an epitaxial semiconductor layer on the substrate; a gate layer on the epitaxial semiconductor layer; and electrical contacts. In some cases, the epitaxial semiconductor layer can comprise a superlattice comprising a first and a second set of layers comprising oxide materials with a first and second bandgap. The gate layer can comprise an oxide material with a third bandgap, wherein the third bandgap is wider than the first bandgap. In some cases, the epitaxial semiconductor layer can comprise a second oxide material with a first bandgap, wherein the second oxide material comprises single crystal A.sub.xB.sub.1-xO.sub.n, wherein 0<x<1.0, wherein A is Al and/or Ga, wherein B is Mg, Ni, a rare earth, Er, Gd, Ir, Bi, or Li.

An air gap forming method of forming an air gap in a gap structure having an upper surface, a lower surface, and a sidewall connecting the upper and lower surface, includes: repeatedly performing a selective deposition cycle, wherein the selective deposition cycle includes supplying a deposition inhibitor onto a substrate including the gap structure; and selectively forming a material layer on the upper surface compared to the sidewall.

A semiconductor manufacturing apparatus according to the present embodiment includes a chamber on which a substrate is placed, a first gas flow path configured to supply a first processing gas into the chamber, a second gas flow path configured to supply a second processing gas into the chamber, a first replacement gas flow path configured to supply a first replacement gas into the chamber, a replacement gas heating unit configured to heat the first replacement gas, a second replacement gas flow path configured to supply a second replacement gas into the chamber, and a replacement gas cooling unit configured to cool the second replacement gas.

A method for manufacturing a metal fluoride-containing organic polymer film includes forming an organic polymer film on a base body. The method includes exposing the organic polymer film to an organometallic compound containing a first metal, thereby infiltrating the organic polymer film with the organometallic compound. The method includes exposing the organic polymer film infiltrated with the organometallic compound to hydrogen fluoride, thereby providing a fluoride of the first metal in the organic polymer film.

A semiconductor device includes a semiconductor layer of a first conductivity type. A well region that is a second conductivity type well region is formed on a surface layer portion of the semiconductor layer and has a channel region defined therein. A source region that is a first conductivity type source region is formed on a surface layer portion of the well region. A gate insulating film is formed on the semiconductor layer and has a multilayer structure. A gate electrode is opposed to the channel region of the well region where a channel is formed through the gate insulating film.