CFET devices having a gate-all-around structure are provided. In one aspect, a method of forming a CFET device includes: forming a nanosheet device stack(s) on a substrate including alternating first/second nanosheets of a first/second material, wherein lower nanosheets in the nanosheet device stack(s) are separated from the substrate and from upper nanosheets in the nanosheet device stack(s) by sacrificial nanosheets; forming a ζ-shaped dielectric spacer separating the lower and upper nanosheets; forming lower/upper source and drains on opposite sides of the lower/upper nanosheets, separated by an isolation spacer; selectively removing the first nanosheets; and forming a first gate surrounding a portion of each of the lower nanosheets including a first workfunction-setting metal(s), and a second gate surrounding a portion of each of the upper nanosheets including a second workfunction-setting metal(s), wherein the first and second workfunction-setting metals are separated by the ζ-shaped dielectric spacer. A CFET device is also provided.

Methods of forming semiconductor device with fluorine-incorporated metal nitride films are described. A substrate surface is exposed to a metal fluoride precursor to form a metal-fluorine species on the substrate surface. The substrate surface is exposed to a nitriding agent to react with the metal-fluorine species to form a fluorine-incorporated metal nitride film.

A method for producing a layer covering the first surfaces of a structure and leaving the second surfaces uncovered including a sequence for forming an initial layer by PEALD deposition, the sequence including cycles, each including injections of first and second precursor in a reaction chamber, and plasma formation in the reaction chamber. The cycles are carried out at a temperature T.sub.cycle such that T.sub.cycle ≤ (T.sub.min - 20° C.), T.sub.min being the minimum temperature of a nominal temperature window for a PEALD deposition. The method includes exposing the initial layer to a densification plasma such that the exposure to the ion flow makes the material on the first surfaces more resistant to etching than the material on the second surfaces. The method also includes a selective etching step, such that the initial layer covers the first surfaces of the front face of the structure by leaving the second surfaces uncovered.

A manufacturing method for a semiconductor device includes forming a dielectric film on a semiconductor substrate or on a lower electrode that is formed on a semiconductor substrate, attaching a metal to a predetermined area on a surface of the dielectric film selectively, forming a metal oxide film with an insulation property in the predetermined area on the surface of the dielectric film by applying heat treatment to the metal, and forming an upper electrode on the dielectric film in a state where the metal oxide film is formed in the predetermined area on the surface of the dielectric film.

Techniques to enable bottom barrier free interconnects without voids. In one aspect, a method of forming interconnects includes: forming metal lines embedded in a dielectric; depositing a sacrificial dielectric over the metal lines; patterning vias and trenches in the sacrificial dielectric down to the metal lines, with the trenches positioned over the vias; lining the vias and trenches with a barrier layer; depositing a conductor into the vias and trenches over the barrier layer to form the interconnects; forming a selective capping layer on the interconnects; removing the sacrificial dielectric in its entirety; and depositing an interlayer dielectric (ILD) to replace the sacrificial dielectric. An interconnect structure is also provided.

The present disclosure relates to a film formed with a tantalum-based precursor, as well as methods for forming and employing such films. The film can be employed as a photopatternable film or a radiation-sensitive film. In non-limiting embodiments, the radiation can include extreme ultraviolet (EUV) or deep ultraviolet (DUV) radiation.

A semiconductor device structure is provided. The semiconductor device structure includes a first fin structure and a second fin structure over a semiconductor substrate and a first epitaxial structure over the first fin structure. The semiconductor device structure also includes a second epitaxial structure over the second fin structure. The semiconductor device structure further includes a dielectric fin over the semiconductor substrate. The dielectric fin is between the first fin structure and the second fin structure. The dielectric fin has an inner portion and a protective layer. The protective layer extends along sidewalls and a bottom of the inner portion, and the protective layer has a dielectric constant higher than that of the inner portion.

A method of manufacturing a semiconductor device includes forming a plurality of work function metal layers and an oxygen absorbing layer over a channel region of the semiconductor device, including forming a first work function metal layer over the channel region, forming an oxygen absorbing layer over the first work function metal layer, forming a second work function metal layer over the oxygen absorbing layer. A gate electrode metal layer is formed over the plurality of work function metal layers. The work function metal layers, oxygen absorbing layer, and gate electrode metal layer are made of different materials.

Embodiments of the present invention are directed to forming a sub-stoichiometric metal-oxide film using a modified atomic layer deposition (ALD) process. In a non-limiting embodiment of the invention, a first precursor and a second precursor are selected. The first precursor can include a metal and a first ligand. The second precursor can include the same metal and a second ligand. A substrate can be exposed to the first precursor during a first pulse of an ALD cycle. The substrate can be exposed to the second precursor during a second pulse of the ALD cycle. The second pulse can occur directly after the first pulse without an intervening thermal oxidant. The substrate can be exposed to the thermal oxidant during a third pulse of the ALD cycle.

Embodiments provided herein generally relate to methods of modifying portions of layer stacks. The methods include forming deep trenches and narrow trenches, such that a desirably low voltage drop between layers is achieved. A method of forming a deep trench includes etching portions of a flowable dielectric, such that a deep metal contact is disposed below the deep trench. The deep trench is selectively etched to form a modified deep trench. A method of forming a super via includes forming a super via trench through a second layer stack of a layer superstack. The methods disclosed herein allow for decreasing the resistance, and thus the voltage drop, of features in a semiconductor layer stack.