A semiconductor device with high on-state current and high reliability is provided. The semiconductor device includes first to fifth insulators, first to third oxides, and first to fourth conductors; the fifth insulator includes an opening in which the second oxide is exposed; the third oxide is placed in contact with a bottom portion of the opening and a side portion of the opening; the second insulator is placed in contact with the third oxide; the third conductor is provided in contact with the second insulator; the third insulator is placed in contact with a top surface of the third conductor and the second insulator; the fourth conductor is in contact with the third insulator and the top surface of the third conductor and placed in the opening with the third oxide, the second insulator, and the third insulator therebetween; the fourth insulator is in contact with a top surface of the first insulator, a side surface of the first oxide, a side surface of the second oxide, a side surface of the first conductor, a top surface of the first conductor, a side surface of the second conductor, and a top surface of the second conductor; and the third insulator is less likely to pass oxygen and/or hydrogen than the second insulator.

Methods and apparatus for forming a semiconductor structure such as an NMOS gate electrode are described. Methods may include depositing a first capping layer having a first surface atop a first surface of a high-k dielectric layer; and depositing at least one metal layer having a first surface atop the first surface of the first capping layer, wherein the at least one metal layer includes titanium aluminum silicide material. Some methods include removing an oxide layer from the first surface of the first capping layer by contacting the first capping layer with metal chloride in an amount sufficient to remove an oxide layer. Some methods for depositing a titanium aluminum silicide material are performed by an atomic layer deposition process performed at a temperature of 350 to 400 degrees Celsius.

Structures and methods of forming the same are provided. A structure according to the present disclosure includes an interconnect structure, an aluminum oxide layer over the interconnect structure, and a transistor formed over the aluminum oxide layer. The transistor includes cuprous oxide.

Semiconductor devices and methods of forming the same are provided. A method according to an embodiment includes receiving a substrate including a lower contact feature, depositing a first dielectric layer over a substrate, forming a metal-insulator-metal (MIM) structure over the first dielectric layer, depositing a second dielectric layer over the MIM structure, performing a first etch process to form an opening that extends through the second dielectric layer to expose the MIM structure, performing a second etch process to extend the opening through the MIM structure to expose the first dielectric layer; and performing a third etch process to further extend the opening through the first dielectric layer to expose the lower contact feature. Etchants of the first etch process and the third etch process include fluorine while the etchant of the second etch process is free of fluorine.

Techniques for forming barrierless contacts filled with Co are provided. In one aspect, a method for forming barrierless contacts includes: forming bottom metal contacts in a first ILD; depositing a second ILD on the bottom metal contacts; forming contact vias in the second ILD landing on the bottom metal contacts; selectively forming a liner on a top surface of the second ILD and on the second ILD along sidewalls of the contact vias; filling the contact vias with a metal; and removing an excess of the metal to form the barrierless contacts whereby metal-to-metal contact is present between the barrierless contacts and the bottom metal contacts. A contact structure is also provided.

Embodiments of the present invention are directed to forming a sub-stoichiometric metal-oxide film using a modified atomic layer deposition (ALD) process. In a non-limiting embodiment of the invention, a first precursor and a second precursor are selected. The first precursor can include a metal and a first ligand. The second precursor can include the same metal and a second ligand. A substrate can be exposed to the first precursor during a first pulse of an ALD cycle. The substrate can be exposed to the second precursor during a second pulse of the ALD cycle. The second pulse can occur directly after the first pulse without an intervening thermal oxidant. The substrate can be exposed to the thermal oxidant during a third pulse of the ALD cycle.

A method of adjusting a threshold voltage in a field-effect-transistor (FET) device includes performing a deposition process to deposit a diffusion barrier layer over a gate dielectric layer in a first region, a second region, and a third region of a semiconductor structure, performing a first patterning process to remove a portion of the deposited diffusion layer in the first region, performing a second patterning process to partially remove a portion of the deposited diffusion barrier layer in the second region, performing a dipole layer deposition process to deposit a dipole layer over the gate dielectric layer in the first region, and the diffusion barrier layer in the second region and in the third region, and performing an annealing process to drive dipole dopants from the dipole layer into the gate dielectric layer.

Embodiments of the present invention are directed to forming a sub-stoichiometric metal-oxide film using a modified atomic layer deposition (ALD) process. In a non-limiting embodiment of the invention, a first precursor and a second precursor are selected. The first precursor can include a metal and a first ligand. The second precursor can include the same metal and a second ligand. A substrate can be exposed to the first precursor during a first pulse of an ALD cycle. The substrate can be exposed to the second precursor during a second pulse of the ALD cycle. The second pulse can occur directly after the first pulse without an intervening thermal oxidant. The substrate can be exposed to the thermal oxidant during a third pulse of the ALD cycle.

A semiconductor processing system is provided to form a capacitor dielectric layer in a metal-insulator-metal capacitor. The semiconductor processing system includes a precursor tank configured to generate a precursor gas from a metal organic solid precursor, a processing chamber configured to perform a plasma enhanced chemical vapor deposition, and at least one buffer tank between the precursor tank and the processing chamber. The at least one buffer tank is coupled to the precursor tank via a first pipe and coupled to the processing chamber via a second pipe.

CFET devices having a gate-all-around structure are provided. In one aspect, a method of forming a CFET device includes: forming a nanosheet device stack(s) on a substrate including alternating first/second nanosheets of a first/second material, wherein lower nanosheets in the nanosheet device stack(s) are separated from the substrate and from upper nanosheets in the nanosheet device stack(s) by sacrificial nanosheets; forming a ζ-shaped dielectric spacer separating the lower and upper nanosheets; forming lower/upper source and drains on opposite sides of the lower/upper nanosheets, separated by an isolation spacer; selectively removing the first nanosheets; and forming a first gate surrounding a portion of each of the lower nanosheets including a first workfunction-setting metal(s), and a second gate surrounding a portion of each of the upper nanosheets including a second workfunction-setting metal(s), wherein the first and second workfunction-setting metals are separated by the ζ-shaped dielectric spacer. A CFET device is also provided.